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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aba532832d1sm336935366b.81.2025.02.14.05.10.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 14 Feb 2025 05:10:59 -0800 (PST) Message-ID: <659ba3dd-0991-4660-9dd6-feda682f15e1@oss.qualcomm.com> Date: Fri, 14 Feb 2025 14:10:56 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 1/4] arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties To: Krishna Chaitanya Chundru , Manivannan Sadhasivam , Krishna Chaitanya Chundru Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com References: <20250210-preset_v6-v6-0-cbd837d0028d@oss.qualcomm.com> <20250210-preset_v6-v6-1-cbd837d0028d@oss.qualcomm.com> <20250214084427.5ciy5ks6oypr3dvg@thinkpad> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: vyLg8Oh1_HJwWSNC1D3wIDp5TP5kcfjW X-Proofpoint-ORIG-GUID: vyLg8Oh1_HJwWSNC1D3wIDp5TP5kcfjW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-14_05,2025-02-13_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 adultscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 spamscore=0 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502140097 On 14.02.2025 9:48 AM, Krishna Chaitanya Chundru wrote: > > > On 2/14/2025 2:14 PM, Manivannan Sadhasivam wrote: >> On Mon, Feb 10, 2025 at 01:00:00PM +0530, Krishna Chaitanya Chundru wrote: >>> Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data >>> rates used in lane equalization procedure. >>> >>> Signed-off-by: Krishna Chaitanya Chundru >>> --- >>> This patch depends on the this dt binding pull request which got recently >>> merged: https://github.com/devicetree-org/dt-schema/pull/146 >>> --- >>> --- >>>   arch/arm64/boot/dts/qcom/x1e80100.dtsi | 13 +++++++++++++ >>>   1 file changed, 13 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> index 4936fa5b98ff..1b815d4eed5c 100644 >>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> @@ -3209,6 +3209,11 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >>>               phys = <&pcie3_phy>; >>>               phy-names = "pciephy"; >>>   +            eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>, >>> +                      /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; >> >> Why 2 16bit arrays? >> > Just to keep line length below 100, if I use single line it is crossing > 100 lines. Oh I didn't notice this.. Ideally we would have , , ..., ; But it seems like /bits/ applies individually to each entry? That's a bit weird, but I'll add it to my list of things I don't like about dtc.. Let's do: eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 0x5555 0x5555 0x5555 0x5555>; for now Konrad