From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCEE9227BB9; Wed, 19 Nov 2025 14:31:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763562715; cv=none; b=Wh4ySXY8899JC0ZCY/rpHYGK0zmPwca7C6Sx98WbgW9pT9yeAFsviX7jDYmShZGsftms+Ch5fWVakM/oPGmtbyvEnO6o/zLNVTzl46KtkugOuFsBeNtjkNeaP9sTEbEaBYA+D5ew1Fqwsl6QKFLIiqOcWDP2Qxb2rjH6M3tpSTQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763562715; c=relaxed/simple; bh=t7JHEvub1bQJal+g6fm+oWNxS6WRDvkPwGmxdErav44=; h=MIME-Version:Date:From:To:Cc:Message-Id:In-Reply-To:References: Subject:Content-Type; b=Ymg75ZP1yjaWm7ZaVc0MKrezcZz0Pm58xtM1VgnT/Ji1hj22EJLhJ7fnHqmnYAgHzcM6Vpsz+yqq8gl8po+Sgr5IA8Zx7tv8OJSP8ZGSfGnWFioHrrU9OB4H2mlUD8mOwO6EDdHZRGHGqkUk1tGMhTArSIOKK4514FaTa88ggoo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OtZWl30O; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OtZWl30O" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E4FD5C4AF0B; Wed, 19 Nov 2025 14:31:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763562715; bh=t7JHEvub1bQJal+g6fm+oWNxS6WRDvkPwGmxdErav44=; h=Date:From:To:Cc:In-Reply-To:References:Subject:From; b=OtZWl30OwqZXuRTvfhy8T6wVumbrZWoGCTYDInBW4XmfLWgDkgaJiJZrdS3ZzCUqL JDYIkSCAlSNwQ3IrhV3rISRAPVaQOiTwR4Qva9gSs9IYPdwgqPlnIkhsgQfxU7uCRb 24LIwD/o8cRnOWFRY4Z+NTXYCT07fcCY6SpNfuiYEWIMQ5oM9o1iktT3XuNoUHeI2M 92getoDiEJ44gJCiSqPnNwbWLQcJwZVzGUhlysAlQGvIc2qdycoaS7o0XRiLp/P9N2 z7pq+1gTaEV6YuIKO1UhxoY/cdOa/Qb0xep0DulfN7FqgbU3DQ3BLiYKchggLduCz6 kI2FGfuWG/FsA== Received: from phl-compute-01.internal (phl-compute-01.internal [10.202.2.41]) by mailfauth.phl.internal (Postfix) with ESMTP id 560CFF4008D; Wed, 19 Nov 2025 09:31:51 -0500 (EST) Received: from phl-imap-02 ([10.202.2.81]) by phl-compute-01.internal (MEProxy); Wed, 19 Nov 2025 09:31:51 -0500 X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtdeggddvvdeggeehucetufdoteggodetrf dotffvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfurfetoffkrfgpnffqhgenuceu rghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujf gurhepofggfffhvfevkfgjfhfutgfgsehtqhertdertdejnecuhfhrohhmpedftehnugih ucfnuhhtohhmihhrshhkihdfuceolhhuthhosehkvghrnhgvlhdrohhrgheqnecuggftrf grthhtvghrnhepjeejvddvtdehffdtgfejjeefgefgjeeggfeuteeiuedvtefgfffhvdej iefguedtnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomh eprghnugihodhmvghsmhhtphgruhhthhhpvghrshhonhgrlhhithihqdduudeiudekheei fedvqddvieefudeiiedtkedqlhhuthhopeepkhgvrhhnvghlrdhorhhgsehlihhnuhigrd hluhhtohdruhhspdhnsggprhgtphhtthhopeegkedpmhhouggvpehsmhhtphhouhhtpdhr tghpthhtohepjhgsrghrohhnsegrkhgrmhgrihdrtghomhdprhgtphhtthhopegsphesrg hlihgvnhekrdguvgdprhgtphhtthhopegrrhhnugesrghrnhgusgdruggvpdhrtghpthht ohepuggrvhgvmhesuggrvhgvmhhlohhfthdrnhgvthdprhgtphhtthhopehmrghthhhivg hurdguvghsnhhohigvrhhssegvfhhfihgtihhoshdrtghomhdprhgtphhtthhopegsohhq uhhnrdhfvghnghesghhmrghilhdrtghomhdprhgtphhtthhopehurhgviihkihesghhmrg hilhdrtghomhdprhgtphhtthhopehrohhsthgvughtsehgohhoughmihhsrdhorhhgpdhr tghpthhtohepjhgrnhhnhhesghhoohhglhgvrdgtohhm X-ME-Proxy: Feedback-ID: ieff94742:Fastmail Received: by mailuser.phl.internal (Postfix, from userid 501) id 1FAFE700054; Wed, 19 Nov 2025 09:31:51 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: A2ZwPDH9FoLc Date: Wed, 19 Nov 2025 06:31:30 -0800 From: "Andy Lutomirski" To: "Valentin Schneider" , "Linux Kernel Mailing List" , linux-mm@kvack.org, rcu@vger.kernel.org, "the arch/x86 maintainers" , linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org, linux-trace-kernel@vger.kernel.org Cc: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "Dave Hansen" , "H. Peter Anvin" , "Peter Zijlstra (Intel)" , "Arnaldo Carvalho de Melo" , "Josh Poimboeuf" , "Paolo Bonzini" , "Arnd Bergmann" , "Frederic Weisbecker" , "Paul E. McKenney" , "Jason Baron" , "Steven Rostedt" , "Ard Biesheuvel" , "Sami Tolvanen" , "David S. Miller" , "Neeraj Upadhyay" , "Joel Fernandes" , "Josh Triplett" , "Boqun Feng" , "Uladzislau Rezki" , "Mathieu Desnoyers" , "Mel Gorman" , "Andrew Morton" , "Masahiro Yamada" , "Han Shen" , "Rik van Riel" , "Jann Horn" , "Dan Carpenter" , "Oleg Nesterov" , "Juri Lelli" , "Clark Williams" , "Yair Podemsky" , "Marcelo Tosatti" , "Daniel Wagner" , "Petr Tesarik" , "Shrikanth Hegde" Message-Id: <65ae9404-5d7d-42a3-969e-7e2ceb56c433@app.fastmail.com> In-Reply-To: <20251114151428.1064524-9-vschneid@redhat.com> References: <20251114150133.1056710-1-vschneid@redhat.com> <20251114151428.1064524-9-vschneid@redhat.com> Subject: Re: [RFC PATCH v7 29/31] x86/mm/pti: Implement a TLB flush immediately after a switch to kernel CR3 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Fri, Nov 14, 2025, at 7:14 AM, Valentin Schneider wrote: > Deferring kernel range TLB flushes requires the guarantee that upon > entering the kernel, no stale entry may be accessed. The simplest way = to > provide such a guarantee is to issue an unconditional flush upon switc= hing > to the kernel CR3, as this is the pivoting point where such stale entr= ies > may be accessed. > Doing this together with the PTI CR3 switch has no actual benefit: MOV C= R3 doesn=E2=80=99t flush global pages. And doing this in asm is pretty g= ross. We don=E2=80=99t even get a free sync_core() out of it because IN= VPCID is not documented as being serializing. Why can=E2=80=99t we do it in C? What=E2=80=99s the actual risk? In or= der to trip over a stale TLB entry, we would need to deference a pointer= to newly allocated kernel virtual memory that was not valid prior to ou= r entry into user mode. I can imagine BPF doing this, but plain noinstr = C in the entry path? Especially noinstr C *that has RCU disabled*? We = already can=E2=80=99t follow an RCU pointer, and ISTM the only style of = kernel code that might do this would use RCU to protect the pointer, and= we are already doomed if we follow an RCU pointer to any sort of memory. We do need to watch out for NMI/MCE hitting before we flush.