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From: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
To: Dmitry Baryshkov <lumag@kernel.org>
Cc: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
	Marijn Suijten <marijn.suijten@somainline.org>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Abhinav Kumar <quic_abhinavk@quicinc.com>,
	Abhinav Kumar <abhinav.kumar@oss.qualcomm.com>,
	linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/5] drm/msm/dpu: Filter writeback modes using writeback maxlinewidth
Date: Thu, 15 May 2025 17:48:09 -0700	[thread overview]
Message-ID: <65cb9653-e315-4b8c-ad21-14cabb7d2ac0@oss.qualcomm.com> (raw)
In-Reply-To: <CALT56yPxcsLhA2eigirjvNiWR5JBFW4jsOAi7QWkgmJgbMnKXw@mail.gmail.com>



On 5/14/2025 5:17 PM, Dmitry Baryshkov wrote:
> On Thu, 15 May 2025 at 02:52, Jessica Zhang
> <jessica.zhang@oss.qualcomm.com> wrote:
>>
>> Since the max mixer width is not a strict hardware limit, use the actual
> 
> Is it? What is the actual max width that the mixer can support?

Hi Dmitry,

By hardware limit, I mean restrictions based on the size of buffers 
within the hardware block itself.

PINGPONG, DSC encoder, and WB blocks all have buffers, so they do have a 
max supported width based on the size of their hardware buffers. On the 
other hand, LM doesn't so it isn't necessarily restricted by a max width.

I can clarify this in the commit message and cover letter.

Thanks,

Jessica Zhang

> 
>> hardware limit (the writeback maxlinewidth) to filter modes.
>>
>> Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
>> ---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c | 9 +--------
>>   1 file changed, 1 insertion(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c
>> index 8ff496082902..0a198896f656 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c
>> @@ -14,14 +14,7 @@ static int dpu_wb_conn_get_modes(struct drm_connector *connector)
>>          struct msm_drm_private *priv = dev->dev_private;
>>          struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
>>
>> -       /*
>> -        * We should ideally be limiting the modes only to the maxlinewidth but
>> -        * on some chipsets this will allow even 4k modes to be added which will
>> -        * fail the per SSPP bandwidth checks. So, till we have dual-SSPP support
>> -        * and source split support added lets limit the modes based on max_mixer_width
>> -        * as 4K modes can then be supported.
>> -        */
>> -       return drm_add_modes_noedid(connector, dpu_kms->catalog->caps->max_mixer_width,
>> +       return drm_add_modes_noedid(connector, dpu_kms->catalog->wb->maxlinewidth,
>>                          dev->mode_config.max_height);
>>   }
>>
>>
>> --
>> 2.49.0
>>


  reply	other threads:[~2025-05-16  0:48 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-14 23:52 [PATCH 0/5] drm/msm/dpu: Drop max_mixer_width and MAX_HDISPLAY_SPLIT Jessica Zhang
2025-05-14 23:52 ` [PATCH 1/5] drm/msm/dpu: Drop maxwidth from dpu_lm_sub_blks struct Jessica Zhang
2025-05-15  0:32   ` Dmitry Baryshkov
2025-05-14 23:52 ` [PATCH 2/5] drm/msm/dpu: Add max pingpong and dsc width to HW catalog Jessica Zhang
2025-05-15  0:21   ` Dmitry Baryshkov
2025-05-15 17:13     ` Jessica Zhang
2025-05-14 23:52 ` [PATCH 3/5] drm/msm/dpu: Check mode against PINGPONG or DSC max width Jessica Zhang
2025-05-15  0:28   ` Dmitry Baryshkov
2025-05-16  0:39     ` Jessica Zhang
2025-05-16 16:19       ` Dmitry Baryshkov
2025-12-31  8:30   ` Xilin Wu
2026-01-03 17:43     ` Dmitry Baryshkov
2025-05-14 23:52 ` [PATCH 4/5] drm/msm/dpu: Filter writeback modes using writeback maxlinewidth Jessica Zhang
2025-05-15  0:17   ` Dmitry Baryshkov
2025-05-16  0:48     ` Jessica Zhang [this message]
2025-05-16 21:40       ` Dmitry Baryshkov
2025-05-14 23:52 ` [PATCH 5/5] drm/msm/dpu: Remove max_mixer_width from catalog Jessica Zhang
2025-05-15  0:32   ` Dmitry Baryshkov

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