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From: Marek Vasut <marek.vasut@mailbox.org>
To: Joseph Guo <qijian.guo@nxp.com>, dri-devel@lists.freedesktop.org
Cc: Andrzej Hajda <andrzej.hajda@intel.com>,
	Conor Dooley <conor+dt@kernel.org>,
	David Airlie <airlied@gmail.com>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	Jonas Karlman <jonas@kwiboo.se>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Rob Herring <robh@kernel.org>, Robert Foss <rfoss@kernel.org>,
	Simona Vetter <simona@ffwll.ch>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org
Subject: Re: [EXT] [PATCH 2/2] drm/bridge: waveshare-dsi: Add support for 1..4 DSI data lanes
Date: Tue, 13 Jan 2026 09:04:17 +0100	[thread overview]
Message-ID: <65ccfeb6-4962-4964-be1d-cfb0ed41773e@mailbox.org> (raw)
In-Reply-To: <773b6e43-4f86-4b11-8e6b-a9f2561a75de@nxp.com>

On 1/13/26 7:41 AM, Joseph Guo wrote:
> On 1/13/2026 7:47 AM, Marek Vasut wrote:
>> [You don't often get email from marek.vasut+renesas@mailbox.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>
>> Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button
>>
>>
>> Parse the data lane count out of DT. Limit the supported data lanes
>> to 1..4 which is the maximum available DSI pairs on the connector of
>> any known panels which may use this bridge. Internally, this bridge
>> is an ChipOne ICN6211 which loads its register configuration from a
>> dedicated storage and its I2C does not seem to be accessible. The
>> ICN6211 also supports up to 4 DSI lanes, so this is a hard limit.
>>
>> To avoid any breakage on old DTs where the parsing of data lanes from
>> DT may fail, fall back to the original hard-coded value of 2 lanes and
>> warn user.
>>
>> The lane configuration is preconfigured in the bridge for each of the
>> WaveShare panels. The 13.3" DSI panel works with 4-lane configuration,
>> others seem to use 2-lane configuration. This is a hardware property,
>> so the actual count should come from DT.
>>
>>
> Hi Marek,
> 
> I don't have 4 lanes waveshare panel on my hands. Have you tested with the 4-lane panel already?
Yes, the 13.3" DSI panel is 4-lane 
https://www.waveshare.com/13.3inch-dsi-lcd.htm , I have it connected to 
Retronix Sparrow Hawk board which has 4-lane port.

See also this patch I submitted, that is the DT binding for it:

[PATCH 2/2] arm64: dts: renesas: sparrow-hawk: Add overlay for WaveShare 
Display 13.3"

  reply	other threads:[~2026-01-13  8:04 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-12 23:47 [PATCH 1/2] dt-bindings: display: bridge: waveshare,dsi2dpi: Document 1..4 DSI lane support Marek Vasut
2026-01-12 23:47 ` [PATCH 2/2] drm/bridge: waveshare-dsi: Add support for 1..4 DSI data lanes Marek Vasut
2026-01-13  6:41   ` [EXT] " Joseph Guo
2026-01-13  8:04     ` Marek Vasut [this message]
2026-01-13  8:15       ` Joseph Guo
2026-01-13  9:15         ` Marek Vasut
2026-01-14  9:32   ` Geert Uytterhoeven
2026-01-15  2:47     ` Marek Vasut

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