From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB3FA3595B; Mon, 9 Dec 2024 12:59:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733749194; cv=none; b=ifGXOF6NYvLyTnaKozoKgr35ni7O44HokiVHoj+ucbzZ8t6EdSl+Czvnvs5Gk7DLZdYNm3Z9t0SFYAJfV5oaHl6HHDG/YnCpQF/q5GWLHlghbJypBnEinoU1sFBeR0G0qyP41nANWbelMaEQvUfywLGuwyoXzPF5RXjYodpgmSE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733749194; c=relaxed/simple; bh=4QW5Bw+ZPeDBkia0tJJgILsd2cHE+S732zb/R+UqnzE=; h=Message-ID:Date:MIME-Version:Subject:To:CC:References:From: In-Reply-To:Content-Type; b=KqESxw7VjAl5B81eNPfRfNf9FZeFuUbwKbe2e5vrIe5ksiGPQ8qCipxwyxECfErVkYF0L2ecStfrbyLaMvE4Fa7xQvbJMWhZyF8HbaWlh7lu9g3b/zAVR3VRYzCaJGgs3Aqn5V5hFrlD+eQBq7hpunhL9F0Y651Krkruw17eNro= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=K3Q6sXoL; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="K3Q6sXoL" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B98Lbam014059; Mon, 9 Dec 2024 12:59:44 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= OxUmyy6yV13PBzRPg/BfEY5/02n3djkRn3ZTbxgOHW0=; b=K3Q6sXoLG6VOJO2y sYvzhsZpm0js41vDNd7CnnEDPqav0MDrITVU5FyhWKfJrqb3ve2fCPjZVDz752sd QQ3FRbQq/qWAvDOP0VMIQTr8R6h7Ybb/Td3hULAEaqP5JIT+b2p9z8jqOQElS1AT FA/xgwZJ248IchUt6u276+PU45kxlWzXMTaJfcjdCKF6w0cKKNW5iNsqvM1KfISb SE8+SSjA+CAIWfq615r4908LSbZo0SIzdI+kjFnx2q/XKy5tWMA8u2ZNEWXRFNLI VMIyP+c8CW+ViC2d/vaV7ZCaQ3xMgyUzU6/LMZJF9qoyYEkFHBwesUm3ct8mcP30 BtRJ0Q== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43dvyah149-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 09 Dec 2024 12:59:43 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B9CxgSH005482 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 9 Dec 2024 12:59:42 GMT Received: from [10.216.3.14] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 9 Dec 2024 04:59:37 -0800 Message-ID: <65d4378a-43f0-49ac-a47d-c700ae5e7de1@quicinc.com> Date: Mon, 9 Dec 2024 18:29:34 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 5/7] drm/msm: adreno: enable GMU bandwidth for A740 and A750 To: Neil Armstrong , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , "Dmitry Baryshkov" , Marijn Suijten , David Airlie , "Simona Vetter" , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , References: <20241205-topic-sm8x50-gpu-bw-vote-v4-0-9650d15dd435@linaro.org> <20241205-topic-sm8x50-gpu-bw-vote-v4-5-9650d15dd435@linaro.org> Content-Language: en-US From: Akhil P Oommen In-Reply-To: <20241205-topic-sm8x50-gpu-bw-vote-v4-5-9650d15dd435@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: pVrhNiBgx-6N8iGdb0DuKBuyyuHFR68Q X-Proofpoint-ORIG-GUID: pVrhNiBgx-6N8iGdb0DuKBuyyuHFR68Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 suspectscore=0 clxscore=1015 malwarescore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412090102 On 12/5/2024 8:31 PM, Neil Armstrong wrote: > Now all the DDR bandwidth voting via the GPU Management Unit (GMU) > is in place, declare the Bus Control Modules (BCMs) and the > corresponding parameters in the GPU info struct. > > Reviewed-by: Dmitry Baryshkov > Signed-off-by: Neil Armstrong Reviewed-by: Akhil P Oommen -Akhil > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..edffb7737a97b268bb2986d557969e651988a344 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -1388,6 +1388,17 @@ static const struct adreno_info a7xx_gpus[] = { > .pwrup_reglist = &a7xx_pwrup_reglist, > .gmu_chipid = 0x7020100, > .gmu_cgc_mode = 0x00020202, > + .bcms = (const struct a6xx_bcm[]) { > + { .name = "SH0", .buswidth = 16 }, > + { .name = "MC0", .buswidth = 4 }, > + { > + .name = "ACV", > + .fixed = true, > + .perfmode = BIT(3), > + .perfmode_bw = 16500000, > + }, > + { /* sentinel */ }, > + }, > }, > .address_space_size = SZ_16G, > .preempt_record_size = 4192 * SZ_1K, > @@ -1432,6 +1443,17 @@ static const struct adreno_info a7xx_gpus[] = { > .pwrup_reglist = &a7xx_pwrup_reglist, > .gmu_chipid = 0x7090100, > .gmu_cgc_mode = 0x00020202, > + .bcms = (const struct a6xx_bcm[]) { > + { .name = "SH0", .buswidth = 16 }, > + { .name = "MC0", .buswidth = 4 }, > + { > + .name = "ACV", > + .fixed = true, > + .perfmode = BIT(2), > + .perfmode_bw = 10687500, > + }, > + { /* sentinel */ }, > + }, > }, > .address_space_size = SZ_16G, > .preempt_record_size = 3572 * SZ_1K, >