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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: rGfK_4IrRksY5VUAt8mAyo9kc3a5PRFE X-Authority-Analysis: v=2.4 cv=dPczC+Zb c=1 sm=1 tr=0 ts=6ab0f5a1 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=DFGctsAPzAe98lL7n_0A:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIxMDEzMSBTYWx0ZWRfX4g14ImY9uJ5X ONy6yZqGFtbQ/CRjzEXbNVdLk+LlWOiS/LfFq3UDH4VN6S1GXPj42CUhhLk0qLBVNIQ+miATANi N4bZBhZVuwP08n5U7NNtVz4DnFhx72dnGxMIQ5mTV2S2rtBF1vCK2RxVez29WNm7nYrIeWrMSzq d4uRCLJnyPcDFifiJvrQZGNteoDP9eP1YXPtF9UeiS5vPDlfMlffPsZ7M4JMUqGY/HPNZwn610f 7X9YYFL2/+DUaftIr4xGH+PlJYByauCf0aBpXwe2+s6Cyw2RnY/fsWFpNv7P/FiV7sozXk0e2iV CxBxS1JgCSXaJr98PVygc37W4/X7Q44vmb07WpR3R1h0vBULb2ROEY6r08rzcTG/XCx7Ccx9Uo5 f30HARb+opvDV/QF1z5BP6VQFvlPilmReRvGJoR3pFTUSUlWAHVkwvjZyM4anOw1qGr8Z+d40FS 4+ODext1vW7oRKF6H+Q== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIxMDEzMSBTYWx0ZWRfX7B9Hc1o771gg 9Jmya6gznIaJiGfuZo9iWWS76ML91SGjr2rcKVt9OBQBrzcpVD2jjxRGXe3gniQvVAfhJmfzHNm 3n1GlJpWNCtcuquWGf3qCjl2+pF5M/E= X-Proofpoint-ORIG-GUID: rGfK_4IrRksY5VUAt8mAyo9kc3a5PRFE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-21_03,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 adultscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609210131 On 9/16/2026 11:34 AM, Qiang Yu wrote: > The controller now calls phy_init() from > qcom_pcie_host_init()/qcom_pcie_enable_resources() and phy_reset() > from inside its own core reset assert/deassert, so the PHY's reset > toggles alongside the controller's core reset as HPG requires. > Making that actually happen here needs phy_ops::init and > phy_ops::reset implemented, and phy_ops::power_on adjusted to match. > Split the combined phy_ops::power_on/power_off into > phy_ops::init/exit/reset/power_on to do that. > > phy_ops::init enables regulators and all clocks (pipe clock first) > and determines skip_init/skip_reset. phy_ops::reset toggles the > reset that skip_init picked. Register-table programming used to run > while the no-CSR reset was still asserted; now it runs afterwards, > in phy_ops::power_on. > > Adds skip_reset to struct qmp_pcie so phy_ops::reset and > phy_ops::power_on share the value phy_ops::init determined instead > of re-reading PCS registers. > > Signed-off-by: Qiang Yu > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 184 ++++++++++++++----------------- > 1 file changed, 80 insertions(+), 104 deletions(-) Verified the PCIe enumeration in IPQ9574 and IPQ5424 and it works fine. So, Tested-by: Kathiravan Thirumoorthy #IPQ9574-RDP433, IPQ5424-RDP466