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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76e4558a81asm629191b3a.83.2025.08.15.01.25.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 Aug 2025 01:25:53 -0700 (PDT) Message-ID: <661789d6-5fbe-4915-b70a-5ff2466c7a26@oss.qualcomm.com> Date: Fri, 15 Aug 2025 16:25:43 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 02/13] dt-bindings: phy: Add binding for QCS615 standalone QMP DP PHY To: Krzysztof Kozlowski , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, fange.zhang@oss.qualcomm.com, quic_lliu6@quicinc.com, quic_yongmou@quicinc.com References: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> <20250722-add-displayport-support-for-qcs615-platform-v2-2-42b4037171f8@oss.qualcomm.com> <0c94206c-f70f-4bed-81ec-bb2870748121@kernel.org> From: Xiangxu Yin In-Reply-To: <0c94206c-f70f-4bed-81ec-bb2870748121@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=G6EcE8k5 c=1 sm=1 tr=0 ts=689eef13 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=P-IC7800AAAA:8 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=0gnJL556ed7yCVVD25sA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 a=d3PnA9EDa4IxuAV0gXij:22 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA5NyBTYWx0ZWRfXzD6olhmEmyUy hgMkj37Y9uJOUuLYC2/y0KhLk6pTvQPA7FilDT4Kx1wrQq69DhdNlhv4Qm0frmA/gSijqOclaQU QzzbBbsbu4IRhCmXdJdpjK9KV/G1yUu2cZGBs4gdVlhdUAGxAPaxnTu2OX7ht7uo3ZPKGFKqW40 SIzEjhRg/R4UjohOkpLsPGL7vWVbeyhhszjQVv98H4mXuz7fqirFPBzJSV1/giMJ2u0+svixy93 imcrIu46RCXjK4GTVga/iXqvLcUPWHmuJBe5rcCSldC5HlYMLP8uqRQJE15Ojh4D8GfYOd/keWP 1vYL9aiBj1TCUezqR9fglK5WnuWx0iQvxyl2rmHmWTs1zeZDEFqLagwx9vYQGSq5S3fpWepsyCx 6xePbzV7 X-Proofpoint-ORIG-GUID: mPGlrxi2nknyrf4JeIBy4KYFwP2WVBvs X-Proofpoint-GUID: mPGlrxi2nknyrf4JeIBy4KYFwP2WVBvs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-15_03,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 phishscore=0 malwarescore=0 adultscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110097 On 7/22/2025 5:18 PM, Krzysztof Kozlowski wrote: > On 22/07/2025 09:22, Xiangxu Yin wrote: >> Introduce device tree binding documentation for the Qualcomm QMP DP PHY >> on QCS615 SoCs. This PHY supports DisplayPort functionality and is >> designed to operate independently from the USB3 PHY. > A nit, subject: drop second/last, redundant "binding for". The > "dt-bindings" prefix is already stating that these are bindings. > See also: > https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18 Ok, will update subject in next patch. >> Unlike combo PHYs found on other platforms, the QCS615 DP PHY is >> standalone and does not support USB/DP multiplexing. The binding >> describes the required clocks, resets, TCSR configuration, and clock/PHY >> cells for proper integration. >> >> Signed-off-by: Xiangxu Yin >> --- >> .../bindings/phy/qcom,qcs615-qmp-dp-phy.yaml | 111 +++++++++++++++++++++ >> 1 file changed, 111 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-dp-phy.yaml >> new file mode 100644 >> index 0000000000000000000000000000000000000000..17e37c1df7b61dc2f7aa35ee106fd94ee2829c5f >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-dp-phy.yaml >> @@ -0,0 +1,111 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-dp-phy.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm QMP PHY controller (DP, QCS615) > That's too vague title. You are not adding here Qualcomm QMP PHY > controllers. Will update to 'Qualcomm QMP USB3-DP PHY controller (DP, QCS615)' in next patch. > >> + >> +maintainers: >> + - Vinod Koul > Hm? Why? I referred to the definitions in qcom,msm8998-qmp-usb3-phy.yaml and qcom,sc8280xp-qmp-usb43dp-phy.yaml. I also found that Vinod Koul is listed as the maintainer of the GENERIC PHY FRAMEWORK in linux-next/MAINTAINERS. Did I misunderstand anything here? >> + >> +description: >> + The QMP DP PHY controller supports DisplayPort physical layer functionality >> + on Qualcomm QCS615 SoCs. This PHY is independent from USB3 PHY and does not >> + support combo mode. >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,qcs615-qmp-dp-phy >> + >> + reg: >> + maxItems: 4 > I don't understand what you are doing here. Why previous patch evolved > into this? Where is any reasoning for that in the changelog? You said: > > "- Add new binding qcom,qcs615-qmp-dp-phy.yaml for QCS615 standalone DP > [Krzysztof]" > > but you must say WHY you are doing things... > > Anyway, missing constraints. Look at other Qualcomm bindings. I misunderstood your earlier comment in '20241129-add-displayport-support-for-qcs615-platform-v1-2-09a4338d93ef@quicinc.com' and mistakenly included "[Krzysztof]" in the commit message as if it were a quote.  Apologies for the confusion and will drop this part in cover letter in next patch. In next patch, the address regions will be consolidated into a single range, similar to other QMP PHYs, and |maxItems| will be updated to |1|. > >> + >> + clocks: >> + maxItems: 2 >> + >> + clock-names: >> + items: >> + - const: cfg_ahb >> + - const: ref >> + >> + clock-output-names: >> + maxItems: 2 >> + description: >> + Names of the clocks provided by the PHY. > Drop description, redundant. It cannot be anything else. Ok, will drop it. > >> + >> + qcom,tcsr-reg: >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + items: >> + - items: >> + - description: phandle to TCSR hardware block >> + - description: offset of the DP PHY moode register >> + description: >> + DP PHY moode register present in the TCSR >> + >> + resets: >> + maxItems: 1 >> + >> + reset-names: >> + items: >> + - const: phy > Drop reset-names, useless. In next patch, this config will be updated to USB or DP PHY binding with two resets: 'phy_phy' for USB and 'dp_phy' for DP. Shall I keep 'reset-names' prop here? > >> + >> + vdda-phy-supply: true >> + >> + vdda-pll-supply: true >> + >> + "#clock-cells": >> + const: 1 >> + description: >> + See include/dt-bindings/phy/phy-qcom-qmp.h >> + >> + "#phy-cells": >> + const: 1 >> + description: >> + See include/dt-bindings/phy/phy-qcom-qmp.h >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - clock-output-names >> + - qcom,tcsr-reg >> + - resets >> + - reset-names >> + - vdda-phy-supply >> + - vdda-pll-supply >> + - "#clock-cells" >> + - "#phy-cells" >> + > Why introducing completely different order? See existing binding and DTS > coding style. > > Best regards, > Krzysztof Ok, will update to follow the existing order. compatible reg clocks clock-names resets reset-names vdda-phy-supply vdda-pll-supply #clock-cells #phy-cells qcom,tcsr-reg