From: George Zhang <george.zhang@amd.com>
To: Jackie Dong <xy-jackie@139.com>,
harry.wentland@amd.com, sunpeng.li@amd.com, siqueira@igalia.com,
alexander.deucher@amd.com, christian.koenig@amd.com,
airlied@gmail.com, simona@ffwll.ch, alex.hung@amd.com,
ivan.lipski@amd.com, wenjing.liu@amd.com, robin.chen@amd.com,
superm1@kernel.org, meenakshikumar.somasundaram@amd.com,
Derek.Lai@amd.com, wei-guang.li@amd.com,
gaghik.khachatrian@amd.com, jack.chang@amd.com,
Duncan.Ma@amd.com, PeiChen.Huang@amd.com,
aurabindo.pillai@amd.com, zhao.xichao@vivo.com
Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
linux-kernel@vger.kernel.org, Mark.Broadworth@amd.com
Subject: Re: [PATCH] drm/amd/display:Check dp_128b_132b_supported_link_rates.raw before link_rate setting
Date: Fri, 17 Jul 2026 16:15:37 -0400 [thread overview]
Message-ID: <6623e957-6c78-4ec7-83fe-10fddd752aa0@amd.com> (raw)
In-Reply-To: <20260630145955.13994-1-xy-jackie@139.com>
Hi Jackie,
This patch causes a regression when used with LG UltraGear 4K144 (DP),
connected to Realtek DP2 USB-C hub. It is expected to be connecting at
UHBR link rate, but we are observing HBR3 instead.
Thanks,
George
cc: Mark.Broadworth@amd.com
On 6/30/26 10:59, Jackie Dong wrote:
> [WHY]
> In the evolution of displays from DP 1.4 to DP 2.0, due to considerations
> some factors,such as cost, some displays support 128b/132b encoding but
> do not support UHBR rate transmission. The values can be read from DPCD
> register address as below.
>
> 0x00006 is 03
> 0x02215 is 00
>
> For such displays, the current kernel reports the following error message.
>
> [drm:dp_retrieve_lttpr_cap [amdgpu]] *ERROR* retrieve_link_cap: Invalid RX
> 128b_132b_supported_link_rates
>
> [HOW]
> Add new judgment: if all bits in dp_128b_132b_supported_link_rates.raw
> are non-zero, then further determine the specific UHBR type; otherwise,
> determine that the display does not support UHBR.
>
> Signed-off-by: Jackie Dong <xy-jackie@139.com>
> ---
> .../gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
> index 47abb4066709..58cbb7ac8f9e 100644
> --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
> +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
> @@ -2079,7 +2079,8 @@ static bool retrieve_link_cap(struct dc_link *link)
> if (!dpcd_read_sink_ext_caps(link))
> link->dpcd_sink_ext_caps.raw = 0;
>
> - if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
> + if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED &&
> + link->dpcd_caps.dp_128b_132b_supported_link_rates.raw) {
> DC_LOG_DP2("128b/132b encoding is supported at link %d", link->link_index);
>
> /* Read 128b/132b suppoerted link rates */
prev parent reply other threads:[~2026-07-17 20:15 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-30 14:59 Jackie Dong
2026-07-17 20:15 ` George Zhang [this message]
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