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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SN1PEPF00036F41.mail.protection.outlook.com (10.167.248.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9769.17 via Frontend Transport; Mon, 13 Apr 2026 19:43:08 +0000 Received: from nigeria-2635-os.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Mon, 13 Apr 2026 14:43:05 -0500 From: Ashish Kalra To: , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 2/7] x86/msr: add wrmsrq_on_cpus helper Date: Mon, 13 Apr 2026 19:42:41 +0000 Message-ID: <662ddafc74fa90be6fdf7dba09bccc53f821f328.1775874970.git.ashish.kalra@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F41:EE_|SA1PR12MB7412:EE_ X-MS-Office365-Filtering-Correlation-Id: 5aa0cd15-9479-422c-ac4b-08de9994e37a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|7416014|376014|82310400026|1800799024|921020|18002099003|56012099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HBbPw4tr9ZjkVcSqy95nO36Txdo5PfjkLbJHclanm32YGXPdFoIR+YPMUlRUor6jlfccpZ4CzSySsJJCvZCfi11vAwdOvhosfaEJOixYBMAsB6Cs74gYhhGDNOp5fwX62OitN6NhuM65FG/dCy/7q9RbF7vNUcIXsXBaAZKiYFiUuhvpxwD91tgAw87Wgah7RPkdy8p8VmWb2EeirBodcaSSY+qaKX8O7B+Fwxq1vMZFKo6fMCtH6sItOUMBXmh39gIf6yWFGxzYBRLH6UxkcmdXMY1n1Q5v393bmcTIFGW+3DdHPnYuc+maTMPh8O9o0ugtp7gBEPzimlOcsVy16viS5PLcYcyhQNHtBVzs1Khfjkkhi0OM4NggMhc9NBaIkIblWjp2/jSHCm7oo/oiwO0pxIcjdBnLsmWSVQ5/oTiQngeY1jq3/fV6VFWezKrM X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2026 19:43:08.3212 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5aa0cd15-9479-422c-ac4b-08de9994e37a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F41.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7412 From: Ashish Kalra The existing wrmsr_on_cpus() takes a per-cpu struct msr array, requiring callers to allocate and populate per-cpu storage even when every CPU receives the same value. This is unnecessary overhead for the common case of writing a single uniform u64 to a per-CPU MSR across multiple CPUs. Add wrmsrq_on_cpus() which writes the same u64 value to the specified MSR on all CPUs in the given cpumask. Co-developed-by: Dave Hansen Signed-off-by: Dave Hansen Signed-off-by: Ashish Kalra --- arch/x86/include/asm/msr.h | 5 +++++ arch/x86/lib/msr-smp.c | 20 ++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 9c2ea29e12a9..f5f63b4115c8 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -260,6 +260,7 @@ int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q); +void wrmsrq_on_cpus(const struct cpumask *mask, u32 msr_no, u64 q); void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __percpu *msrs); void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __percpu *msrs); int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); @@ -289,6 +290,10 @@ static inline int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q) wrmsrq(msr_no, q); return 0; } +static inline void wrmsrq_on_cpus(const struct cpumask *mask, u32 msr_no, u64 q) +{ + wrmsrq_on_cpu(0, msr_no, q); +} static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, struct msr __percpu *msrs) { diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index b8f63419e6ae..d2c91c9bb47b 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -94,6 +94,26 @@ int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q) } EXPORT_SYMBOL(wrmsrq_on_cpu); +void wrmsrq_on_cpus(const struct cpumask *mask, u32 msr_no, u64 q) +{ + struct msr_info rv; + int this_cpu; + + memset(&rv, 0, sizeof(rv)); + + rv.msr_no = msr_no; + rv.reg.q = q; + + this_cpu = get_cpu(); + + if (cpumask_test_cpu(this_cpu, mask)) + __wrmsr_on_cpu(&rv); + + smp_call_function_many(mask, __wrmsr_on_cpu, &rv, 1); + put_cpu(); +} +EXPORT_SYMBOL(wrmsrq_on_cpus); + static void __rwmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __percpu *msrs, void (*msr_func) (void *info)) -- 2.43.0