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Thu, 30 Apr 2026 01:09:46 -0700 (PDT) X-Received: by 2002:a05:6a20:3ca2:b0:3a2:ebfc:6bee with SMTP id adf61e73a8af0-3a3cf86d7c6mr2289285637.41.1777536585696; Thu, 30 Apr 2026 01:09:45 -0700 (PDT) Received: from [10.0.0.4] ([106.222.229.64]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7fd5bcced4sm4129908a12.0.2026.04.30.01.09.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Apr 2026 01:09:45 -0700 (PDT) Message-ID: <663947c0-b316-59bb-3ea3-d1bf313577af@oss.qualcomm.com> Date: Thu, 30 Apr 2026 13:39:39 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v5 2/5] media: iris: Add hardware power on/off ops for X1P42100 Content-Language: en-US To: Wangao Wang , Bryan O'Donoghue , Vikash Garodia , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue References: <20260429-enable_iris_on_purwa-v5-0-438fa96da248@oss.qualcomm.com> <20260429-enable_iris_on_purwa-v5-2-438fa96da248@oss.qualcomm.com> From: Dikshita Agarwal In-Reply-To: <20260429-enable_iris_on_purwa-v5-2-438fa96da248@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: UZbmHIGb24UJSmdqyqW75wXt6i50y4hH X-Authority-Analysis: v=2.4 cv=aYRRWxot c=1 sm=1 tr=0 ts=69f30e4b cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=sQGdqEwRzC/zEhaLYLcr+w==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=isqJhVKGVgDRGp0WoxgA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDMwMDA3OSBTYWx0ZWRfX0VOQpHb4rVXR LV8Y1CbGLxwysy1K5bWXoyzA8Ilbca/jV/uz05EanBs0QFfcpdrQE9HDJc1/c2jRXJcP5qINkRc hmchc0H6J8jDIHUllDYBl5TXPeKIM8WawojP6euYA8LuOSfFCUoY6zmQmHxUQUNwKX09aRQYLO1 sDfddByd84nMyTdkvuLWI6Yuca39j8tES0KHHaReTXfr61NuaCHwSkIy5Y20PByVkSb4Ei2RBmL tT7bkV52rw61TQ+FmKrRR609bJKOEh6v+leuumegbzLpeMc2o2ECjC8BGTiC056E8+im8uTRdPh QrXUd8j9AjIKNckJlBHSGSG9qLJJG67wMQCiDDNEouWx38hl1UnqoUnR+MWKHzf/uz/vSjhzYnC AqYfabcfKuwIgUzDvoQgHCRJGkng0PUhAGXCVVSx1z0oSz1bU5fxsRSG+KpWcqZhkYiDzNKIh0z PXQ1oH5iFLKtGZO4HBw== X-Proofpoint-ORIG-GUID: UZbmHIGb24UJSmdqyqW75wXt6i50y4hH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-30_02,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604300079 On 4/29/2026 1:13 PM, Wangao Wang wrote: > On X1P42100 the Iris block has an extra BSE clock. Wire this clock into > the power on/off sequence. > > The BSE clock is used to drive the Bin Stream Engine, which is a sub-block > of the video codec hardware responsible for bitstream-level processing. It > is required to be enabled separately from the core clock to ensure proper > codec operation. > > Reviewed-by: Bryan O'Donoghue > Signed-off-by: Wangao Wang > --- > drivers/media/platform/qcom/iris/iris_vpu_common.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c > index 548e5f1727fdb7543f76a1871f17257fa2360733..281b1f54cb962dedbfb0ec96ed3a5aab99b50eb8 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c > @@ -224,6 +224,7 @@ void iris_vpu_power_off_hw(struct iris_core *core) > { > dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false); > iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); > + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); > iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); > iris_disable_unprepare_clock(core, IRIS_HW_CLK); > } > @@ -292,12 +293,18 @@ int iris_vpu_power_on_hw(struct iris_core *core) > if (ret && ret != -ENOENT) > goto err_disable_hw_clock; > > + ret = iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK); > + if (ret && ret != -ENOENT) > + goto err_disable_hw_ahb_clock; > + > ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true); > if (ret) > - goto err_disable_hw_ahb_clock; > + goto err_disable_bse_hw_clock; > > return 0; > > +err_disable_bse_hw_clock: > + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); > err_disable_hw_ahb_clock: > iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); > err_disable_hw_clock: > Reviewed-by: Dikshita Agarwal Thanks, Dikshita