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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59b65d5dd1fsm1012485e87.48.2026.01.06.20.28.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 06 Jan 2026 20:28:29 -0800 (PST) Message-ID: <663e3d61-1be3-4342-9dc0-a07d2b9c238e@linaro.org> Date: Wed, 7 Jan 2026 06:28:27 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] arm64: dts: qcom: talos: Add CCI definitions To: Wenmeng Liu , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Todor Tomov , Bryan O'Donoghue Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org References: <20260106-sm6150_evk-v2-0-bb112cb83d74@oss.qualcomm.com> <20260106-sm6150_evk-v2-2-bb112cb83d74@oss.qualcomm.com> From: Vladimir Zapolskiy In-Reply-To: <20260106-sm6150_evk-v2-2-bb112cb83d74@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 1/6/26 11:39, Wenmeng Liu wrote: > Qualcomm Talos SoC contains single controller, > containing 2 I2C hosts. > > Signed-off-by: Wenmeng Liu > --- > arch/arm64/boot/dts/qcom/talos.dtsi | 72 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 72 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi > index e1dfaff9b6bf8641b19a685e74d60ad4e1e99d41..461a39968d928260828993ff3549aa15fd1870df 100644 > --- a/arch/arm64/boot/dts/qcom/talos.dtsi > +++ b/arch/arm64/boot/dts/qcom/talos.dtsi > @@ -1549,6 +1549,42 @@ tlmm: pinctrl@3100000 { > #interrupt-cells = <2>; > wakeup-parent = <&pdc>; > > + cci_default: cci0-default-state { > + cci_i2c0_default: cci-i2c0-default-pins { > + /* SDA, SCL */ > + pins = "gpio32", "gpio33"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + cci_i2c1_default: cci-i2c1-default-pins { > + /* SDA, SCL */ > + pins = "gpio34", "gpio35"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; > + > + cci_sleep: cci-sleep-state { > + cci_i2c0_sleep: cci-i2c0-sleep-state { > + /* SDA, SCL */ > + pins = "gpio32", "gpio33"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + cci_i2c1_sleep: cci-i2c1-sleep-state { > + /* SDA, SCL */ > + pins = "gpio34", "gpio35"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + }; > + > qup_i2c1_data_clk: qup-i2c1-data-clk-state { > pins = "gpio4", "gpio5"; > function = "qup0"; > @@ -3785,6 +3821,42 @@ videocc: clock-controller@ab00000 { > #power-domain-cells = <1>; > }; > > + cci: cci@ac4a000 { > + compatible = "qcom,sm6150-cci", "qcom,msm8996-cci"; > + > + reg = <0x0 0x0ac4a000 0x0 0x4000>; > + interrupts = ; > + power-domains = <&camcc TITAN_TOP_GDSC>; > + clocks = <&camcc CAM_CC_SOC_AHB_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CCI_CLK>; > + clock-names = "soc_ahb", > + "cpas_ahb", > + "cci"; > + pinctrl-0 = <&cci_default>; > + pinctrl-1 = <&cci_sleep>; > + pinctrl-names = "default", "sleep"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + cci_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cci_i2c1: i2c-bus@1 { > + reg = <1>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > camss: isp@acb3000 { > compatible = "qcom,sm6150-camss"; > > After making the changes asked by Dmitry Reviewed-by: Vladimir Zapolskiy -- Best wishes, Vladimir