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charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN0PR12MB5954.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9a97e9aa-59a8-45a2-2000-08dc79bfc27e X-MS-Exchange-CrossTenant-originalarrivaltime: 21 May 2024 17:59:28.8251 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: G3lv00tRaKA8TC8L84QcY/kRxh+pjI56h8UssAwHjsPeIjyyRSXJbnhUNL5unVPxvN+xyVspsiA0luYg5eXNDg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4402 > On May 21, 2024, at 10:55 AM, Jarkko Sakkinen wrote: >>=20 >> /* >> * TCG SPI flow control is documented in section 6.4 of the spec[1]. In = short, >> @@ -247,7 +249,7 @@ static int tpm_tis_spi_write_bytes(struct tpm_tis_da= ta *data, u32 addr, >> int tpm_tis_spi_init(struct spi_device *spi, struct tpm_tis_spi_phy *phy= , >> int irq, const struct tpm_tis_phy_ops *phy_ops) >> { >> - phy->iobuf =3D devm_kmalloc(&spi->dev, MAX_SPI_FRAMESIZE, GFP_KERNEL); >> + phy->iobuf =3D devm_kmalloc(&spi->dev, MAX_SPI_BUFSIZE, GFP_KERNEL); >=20 > It would better to open code here "SPI_HDRSIZE + MAX_SPI_FRAMESIZE". >=20 > I.e. less cross-referencing and documents better what is going on at > the call site. Sure, will make this change in a v2. -matt=