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From: Val Packett <val@packett.cool>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: "Dmitry Baryshkov" <dmitry.baryshkov@oss.qualcomm.com>,
	manivannan.sadhasivam@oss.qualcomm.com,
	"Rob Clark" <robin.clark@oss.qualcomm.com>,
	"Vignesh Raman" <vignesh.raman@collabora.com>,
	"Valentine Burley" <valentine.burley@collabora.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-msm@vger.kernel.org,
	"David E. Box" <david.e.box@linux.intel.com>,
	"Kai-Heng Feng" <kai.heng.feng@canonical.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	"Heiner Kallweit" <hkallweit1@gmail.com>,
	"Chia-Lin Kao" <acelan.kao@canonical.com>,
	"Bjorn Helgaas" <helgaas@kernel.org>
Subject: Re: [PATCH v2 0/2] PCI/ASPM: Enable ASPM and Clock PM by default on devicetree platforms
Date: Tue, 11 Nov 2025 14:29:57 -0300	[thread overview]
Message-ID: <666481e9-4ce3-415f-bad4-e0b4ccf9a4d2@packett.cool> (raw)
In-Reply-To: <twn5ryedkpv76ph3i7xbovktz3abqszthl6cxhtv6uczbv4ap7@4wrmlczxzjll>

On 11/11/25 7:06 AM, Manivannan Sadhasivam wrote:
> On Tue, Nov 11, 2025 at 04:40:01AM -0300, Val Packett wrote:
>> On 11/11/25 4:19 AM, Manivannan Sadhasivam wrote:
>>> [..]
>>>> Totally unpredictable, could be after 4 minutes or 4 days of uptime.
>>>> Panic-indicator LED not blinking, no reaction to magic SysRq, display image
>>>> frozen, just a complete hang until the watchdog does the reset.
>>> I have KIOXIA SSD on my T14s. I do see some random hang, but I thought those
>>> predate the ASPM enablement as I saw them earlier as well. But even before this
>>> series, we had ASPM enabled for SSDs on Qcom targets (or devices that gets
>>> enumerated during initial bus scan), so it might be that the SSD doesn't support
>>> ASPM well enough.
>> I certainly remember that ASPM *was* enabled by default when I first got
>> this laptop, via the custom way that predates this series.
>>
>> Actually that custom enablement code getting removed was how I discovered it
>> was ASPM related!
>>
>> I pulled linux-next once and suddenly the system became stable!.. and then I
>> noticed +2W of battery drain..
> Because, we only enable L0s and L1 by default and not L1ss.

Back in that short time period between the old code getting removed and 
this series landing, the default behavior was no ASPM at all, I'm pretty 
sure.

Again, with the SK hynix SSD I used back then, I *definitely* saw the 
issue with this series in and no args applied.

> [..]
>> I'm currently using the stock drive: Sandisk Corp PC SN740 NVMe SSD
>> (DRAM-less) [15b7:5015] (rev 01)
> I'm suspecting the L1ss issue with this SSD since you said above that
> next/master works fine until you pass 'pcie_aspm=force'. Could you try the below
> diff with that cmdline option?

I did *not* say that it works fine with no arg!

I said that I've only tested this stock WD SSD with 'force' so far, and 
don't have any data on *this* SSD without 'force' yet.

Now testing with this drive and no arg:

                 LnkCtl: ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+
                         ExtSynch+ ClockPM- AutWidDis- BWInt- AutBWInt- 
FltModeDis-

                 L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
                            T_CommonMode=0us LTR1.2_Threshold=156672ns

Let's see how it goes.

But it sounds very odd that all the SSDs would be to blame and not the 
controller.. Other platforms don't seem to be having this issue. Don't 
Intel and AMD enable L1ss by default?

~val


  reply	other threads:[~2025-11-11 17:30 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-22 16:16 Manivannan Sadhasivam via B4 Relay
2025-09-22 16:16 ` [PATCH v2 1/2] PCI/ASPM: Override the ASPM and Clock PM states set by BIOS for " Manivannan Sadhasivam via B4 Relay
2025-10-14 16:30   ` FUKAUMI Naoki
2025-10-14 18:49     ` Bjorn Helgaas
2025-10-14 23:33       ` Dragan Simic
2025-10-15  6:22         ` Manivannan Sadhasivam
2025-10-15 11:23           ` Diederik de Haas
2025-10-23 18:57           ` Dragan Simic
2025-10-15  6:26       ` Manivannan Sadhasivam
2025-10-15  7:13         ` FUKAUMI Naoki
2025-10-15  7:50           ` Manivannan Sadhasivam
2025-10-15  9:11             ` Shawn Lin
2025-10-15  9:43               ` Manivannan Sadhasivam
2025-10-15  9:46               ` Niklas Cassel
2025-10-15 10:33                 ` Manivannan Sadhasivam
2025-10-15 12:17                   ` Niklas Cassel
2025-10-15 13:00                     ` Shawn Lin
2025-10-15 15:23                       ` Niklas Cassel
2025-10-15 23:30                       ` Bjorn Helgaas
2025-10-16  6:46                         ` Hongxing Zhu
2025-10-17  3:36                         ` Manivannan Sadhasivam
2025-10-17  9:47                           ` Shawn Lin
2025-10-17 10:04                             ` Manivannan Sadhasivam
2025-10-17 12:19                               ` Shawn Lin
2025-10-17 12:54                                 ` Manivannan Sadhasivam
2025-10-17 13:45                                   ` Bjorn Helgaas
2025-10-31  6:21                                     ` Manivannan Sadhasivam
2025-10-15 12:26       ` Diederik de Haas
2025-10-15 22:50         ` Bjorn Helgaas
2025-10-16 17:38           ` Diederik de Haas
2025-10-30 22:14       ` Bjorn Helgaas
2025-10-30 22:16         ` Bjorn Helgaas
2026-01-22 12:12   ` Jon Hunter
2026-01-22 13:17     ` Manivannan Sadhasivam
2026-01-22 13:43       ` Jon Hunter
2026-01-22 14:39         ` Manivannan Sadhasivam
2026-01-22 15:29     ` Bjorn Helgaas
2026-01-22 17:01       ` Manivannan Sadhasivam
2026-01-22 19:14         ` Jon Hunter
2026-01-23 10:55           ` Jon Hunter
2026-01-23 13:56             ` Manivannan Sadhasivam
2026-01-23 14:39               ` Jon Hunter
2026-02-16 14:03               ` Jon Hunter
2026-02-16 14:18                 ` Manivannan Sadhasivam
2026-02-16 14:35                   ` Jon Hunter
2026-02-19 17:42                     ` Jon Hunter
2026-02-26 10:34                       ` Jon Hunter
2026-02-26 11:08                         ` Manivannan Sadhasivam
2026-02-26 16:55                           ` Jon Hunter
2026-03-03 16:27                             ` Manivannan Sadhasivam
2026-02-26 11:16                       ` Manivannan Sadhasivam
2026-02-26 16:52                         ` Jon Hunter
2026-03-03 16:17                           ` Manivannan Sadhasivam
2026-03-06 16:03                             ` Jon Hunter
2026-03-09  8:00                               ` Manivannan Sadhasivam
2026-02-16 17:19         ` Claudiu Beznea
2026-02-18 13:56           ` Manivannan Sadhasivam
2026-05-07 10:25       ` Jon Hunter
2026-05-11  5:18         ` Manivannan Sadhasivam
2026-05-12  9:07           ` Jon Hunter
2026-05-15 14:03             ` Manivannan Sadhasivam
2025-09-22 16:16 ` [PATCH v2 2/2] PCI: qcom: Remove the custom ASPM enablement code Manivannan Sadhasivam via B4 Relay
2025-09-23 23:14 ` [PATCH v2 0/2] PCI/ASPM: Enable ASPM and Clock PM by default on devicetree platforms Bjorn Helgaas
2025-11-08 16:18 ` Dmitry Baryshkov
2025-11-11  6:51   ` Val Packett
2025-11-11  7:19     ` Manivannan Sadhasivam
2025-11-11  7:40       ` Val Packett
2025-11-11 10:06         ` Manivannan Sadhasivam
2025-11-11 17:29           ` Val Packett [this message]
2025-11-13  4:30             ` Val Packett
2025-11-11 23:33     ` Bjorn Helgaas

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