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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab7c4da47f5sm232971266b.70.2025.02.10.10.20.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Feb 2025 10:20:02 -0800 (PST) Message-ID: <666f5917-92d6-4c1d-b172-dc03a38ae46b@oss.qualcomm.com> Date: Mon, 10 Feb 2025 19:20:01 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] arm64: dts: qcom: sm8650: switch to interrupt-cells 4 to add PPI partitions To: neil.armstrong@linaro.org, Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250207-topic-sm8650-pmu-ppi-partition-v1-0-dd3ba17b3eea@linaro.org> <20250207-topic-sm8650-pmu-ppi-partition-v1-1-dd3ba17b3eea@linaro.org> <57c82928-5275-4f6c-b6d0-935dd5080f9b@linaro.org> <5b782e14-5262-49f9-938b-b8c9b8935f6a@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <5b782e14-5262-49f9-938b-b8c9b8935f6a@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 80WXIy4Ac2ni9AR2iuhU5pgbNmLDSzuN X-Proofpoint-ORIG-GUID: 80WXIy4Ac2ni9AR2iuhU5pgbNmLDSzuN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-10_10,2025-02-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 phishscore=0 spamscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 mlxlogscore=690 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502100149 On 10.02.2025 10:27 AM, Neil Armstrong wrote: > On 09/02/2025 15:45, Neil Armstrong wrote: >> On 07/02/2025 21:23, Konrad Dybcio wrote: >>> On 7.02.2025 11:31 AM, Neil Armstrong wrote: >>>> The ARM PMUs shares the same per-cpu (PPI) interrupt, so we need to switch >>>> to interrupt-cells = <4> in the GIC node to allow adding an interrupt >>>> partition map phandle as the 4th cell value for GIC_PPI interrupts. >>>> >>>> Signed-off-by: Neil Armstrong >>>> --- >>> >>> If I'm reading the core right, we can leave the fourth cell >>> uninitialized where it makes no sense >> >> It's not what dtbs_check thinks ! > > And if you don't specify the 4th cell, dtc is not happy at all: > > arch/arm64/boot/dts/qcom/sm8650.dtsi:5302.4-27: Warning (interrupts_property): /soc@0/timer@17420000/frame@1742d000:#interrupt-cells: size is (12), expected multiple of 16 > arch/arm64/boot/dts/qcom/sm8650.dtsi:5302.4-27: Warning (interrupts_property): /soc@0/rsc@17a00000:#interrupt-cells: size is (36), expected multiple of 16 > arch/arm64/boot/dts/qcom/sm8650.dtsi:5302.4-27: Warning (interrupts_property): /soc@0/mmc@8804000:#interrupt-cells: size is (24), expected multiple of 16 > ... > for a good reason, if you specify 4 cells and you specify multiple interrupts the > DT code will split the interrupts entry by interrupts-cells + 1. Right, that's a dumb "feature".. but everyone is kicking down the dtc improvements can down the road indefinitely > > Remember we pass the DT in the DTB format without all the verbosity of DTS, > the properly is only a bunch of u32 blobs we can extract with the help > of the -cells properties of the providers. Which we could/should make dtc autogenerate, eventually Konrad