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[37.33.181.83]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5550b2c4f24sm430368e87.143.2025.06.27.05.37.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Jun 2025 05:37:06 -0700 (PDT) Message-ID: <667ac51f-d19d-4832-9aa6-97d9a86e0068@oss.qualcomm.com> Date: Fri, 27 Jun 2025 15:37:09 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 01/10] clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs To: Taniya Das Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Catalin Marinas , Will Deacon , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20250625-qcs615-mm-v10-clock-controllers-v10-0-ec48255f90d8@quicinc.com> <20250625-qcs615-mm-v10-clock-controllers-v10-1-ec48255f90d8@quicinc.com> <44dddd3f-d2d2-4d4b-831a-21e6d9050445@quicinc.com> Content-Language: en-US From: Dmitry Baryshkov In-Reply-To: <44dddd3f-d2d2-4d4b-831a-21e6d9050445@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI3MDEwNCBTYWx0ZWRfX3xURWfwedHvK KW9O+n4jOxdvrvVXgK+dseru8ff4IY7M6o8Tb4xEOrB3l1TJx/QPjf3E0dhuI0MYpmtB7bjaA/5 QWr0B8w1AA4VlwR4XOXvHYWY/XkyxIPMwcdEx+KpJToEezvjDPg8Vyoa72gPVMVnuQ6gtIBuY5+ d/yZh3g2T4btlYqttax8UmYer1MEfR5Tlt4C/3Pm7x3H1r7utEP54DmCFHZqX3Fww9aF2nhDZpn 0ZQJiw6Fen5FL6U/jaQTCw6jbuxv09A5NcBP+/xlE6yUZEydwFCv5Nm9l4y1DuAi2BRYv7wqUUU /RvutVjiz3s2sXAhsLtvRsYWGC8LaTOxxTU5h8EhvZ4tXfePZ7PmiYqk6sWhc28d7JTZ0ONGj6w l6GHBIoE6PtRwqQtSk+HJo+NldldVZtcNfKIJA0KBn4BFkFHKGinJOVz4BHN0nmHf/Sezj8O X-Authority-Analysis: v=2.4 cv=XPQwSRhE c=1 sm=1 tr=0 ts=685e9074 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=a09MB1VsJqAZHPW3esczKA==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=COk6AnOGAAAA:8 a=-U2GbryNtLgmjeNmToIA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: dcPrtjylwWSa6rlOMi3d5nDDI5_d-pVo X-Proofpoint-ORIG-GUID: dcPrtjylwWSa6rlOMi3d5nDDI5_d-pVo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-27_04,2025-06-26_05,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 suspectscore=0 mlxscore=0 spamscore=0 phishscore=0 malwarescore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506270104 On 27/06/2025 13:13, Taniya Das wrote: > > > On 6/25/2025 5:17 PM, Dmitry Baryshkov wrote: >> On Wed, Jun 25, 2025 at 04:13:26PM +0530, Taniya Das wrote: >>> The alpha PLLs which slew to a new frequency at runtime would require >>> the PLL to calibrate at the mid point of the VCO. Add the new PLL ops >>> which can support the slewing of the PLL to a new frequency. >>> >>> Reviewed-by: Imran Shaik >>> Signed-off-by: Taniya Das >>> --- >>> drivers/clk/qcom/clk-alpha-pll.c | 169 +++++++++++++++++++++++++++++++++++++++ >>> drivers/clk/qcom/clk-alpha-pll.h | 1 + >>> 2 files changed, 170 insertions(+) >>> > >>> + /* >>> + * Dynamic pll update will not support switching frequencies across >>> + * vco ranges. In those cases fall back to normal alpha set rate. >>> + */ >>> + if (curr_vco->val != vco->val) >>> + return clk_alpha_pll_set_rate(hw, rate, parent_rate); >>> + >>> + a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH; >>> + >>> + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); >>> + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), lower_32_bits(a)); >>> + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), upper_32_bits(a)); >> >> We have code that does this in __clk_alpha_pll_set_rate() and now you >> are adding two more copies. Please extract PLL_L_VAL, PLL_ALPHA_VAL and >> PLL_USER_CTL / PLL_VCO_MASK into a helper function. >> > > Dmitry, I was thinking of implementing the following as a reusable > helper since it can be leveraged by most of the functions. I'd > appreciate your suggestions or feedback. The code below looks good to me. Please use 'alpha' instead of 'a'. > > static void clk_alpha_pll_update_configs(struct clk_alpha_pll *pll, > const struct pll_vco *vco, u32 l, u64 a, u32 alpha_width, bool alpha_en) > { > regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); > > if (alpha_width > ALPHA_BITWIDTH) > a <<= alpha_width - ALPHA_BITWIDTH; > > if (alpha_width > 32) > regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), upper_32_bits(a)); > > regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), lower_32_bits(a)); > > if (vco) { > regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), > PLL_VCO_MASK << PLL_VCO_SHIFT, > vco->val << PLL_VCO_SHIFT); > } > > if (alpha_en) > regmap_set_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_ALPHA_EN); > } > > >>> + >>> + /* Ensure that the write above goes before slewing the PLL */ >>> + mb(); >>> + >>> + if (clk_hw_is_enabled(hw)) >>> + return clk_alpha_pll_slew_update(pll); >>> + >>> + return 0; >>> +} >>> + >>> +/* >>> + * Slewing plls should be bought up at frequency which is in the middle of the >>> + * desired VCO range. So after bringing up the pll at calibration freq, set it >>> + * back to desired frequency(that was set by previous clk_set_rate). > >>> >> > -- With best wishes Dmitry