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Thu, 02 Jul 2026 21:53:13 -0700 (PDT) X-Received: by 2002:a05:6a21:697:b0:3bf:e94e:e38d with SMTP id adf61e73a8af0-3bfed472a5cmr10107058637.43.1783054392522; Thu, 02 Jul 2026 21:53:12 -0700 (PDT) Received: from [10.217.222.146] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30f0bb843fasm15565027eec.18.2026.07.02.21.53.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Jul 2026 21:53:11 -0700 (PDT) Message-ID: <66b34158-56cf-402d-9364-2522dfc45d80@oss.qualcomm.com> Date: Fri, 3 Jul 2026 10:23:04 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/5] arm64: dts: qcom: shikra: Add ICE, TRNG and QCE nodes To: Konrad Dybcio , Dmitry Baryshkov , Konrad Dybcio Cc: Herbert Xu , "David S. Miller" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Vinod Koul , Thara Gopinath , Frank Li , Andy Gross , Harshal Dev , linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org References: <20260521-shikra_crypto_changse-v1-0-0154cc9cc0de@oss.qualcomm.com> <20260521-shikra_crypto_changse-v1-5-0154cc9cc0de@oss.qualcomm.com> <55039d7e-34df-4f89-8188-fcb45fdea538@oss.qualcomm.com> <46005937-c1a9-409b-89cf-4b8f592dc5d1@oss.qualcomm.com> Content-Language: en-US From: Kuldeep Singh In-Reply-To: <46005937-c1a9-409b-89cf-4b8f592dc5d1@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzAzMDA0MyBTYWx0ZWRfX7ku/uum/8XC4 j4P5FiOstj+3Aidmr0wblJfkbMRrsG+NRwcyJwcxrGw8LpQPNMJqmFgq+lWLRqyPTQ4VJv12xLF PSix4q1Gy6lKJ90Vbme3hubUHpDAi0Q= X-Proofpoint-ORIG-GUID: _UWTgcktrOAPc5qyrtWSpLEmk9hlPS_6 X-Authority-Analysis: v=2.4 cv=O4wJeh9W c=1 sm=1 tr=0 ts=6a47403a cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=pHORTPgO1eFKx7QcuTIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: _UWTgcktrOAPc5qyrtWSpLEmk9hlPS_6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzAzMDA0MyBTYWx0ZWRfX4lmI7udNSF/5 /OVfHosD2rp+3qjZShzoWDBXff4zwLA7OiUqt/H3ouRu4gKW2LaEvUPft9YQbhaxM+p9UCpYtk2 CNMXfSQ2xBKGSh6iax+4/mBz9BCe0ym6IOOtzH16li2KoN09iS1xltcf85n2jL71qX8i3OWx3Xr Mr88Ve2rf9J/ifq/BdVi/5k9OnbccC51ZMdtEYsahei++fAGtjHhgGy4+uJSNZb3GuhC8h0Civu FWRVVjCdBtRPjvoxzFRI3JLe/9hqDuc+AtG7lmMJ4b6C8HOpwXDqQYuFEpa9FYMaY4mdwI8x1Fa iTHE82keGYhjXkGuQzT0at4yHzht+cH7Y7R+7vr8+x4O8n37y/pt0K/Z/9DH2HO8fasPKouCnho VmjuCceSEeyOhAxMKKVODf4Jtb/wSz2j/84QabEnEWcA6zifo9Ux7GYys0J+dUNyMNfjjqktlrZ fmtn+oo7uMbzBigAlvg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-07-03_01,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 phishscore=0 suspectscore=0 malwarescore=0 spamscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607030043 On 29-06-2026 17:10, Konrad Dybcio wrote: > On 6/8/26 12:09 PM, Kuldeep Singh wrote: >>>> + cryptobam: dma-controller@1b04000 { >>>> + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; >>>> + reg = <0x0 0x01b04000 0x0 0x24000>; >>>> + interrupts = ; >>>> + #dma-cells = <1>; >>>> + iommus = <&apps_smmu 0x84 0x0011>, >>>> + <&apps_smmu 0x86 0x0011>, >>>> + <&apps_smmu 0x92 0x0>, >>>> + <&apps_smmu 0x94 0x0011>, >>> >>> 0x84 / 0x0011 is exactly the same as 0x94 / 0x0011. Likewise 0x96 >>> duplicates 0x86. Drop the duplicate IOMMU specifiers or explain in the >>> commit message why they are required. >> >> +Konrad too as there was same discussion in past too. >> >> 0x84/0x94 and 0x86/0x96 pairs are actually different even though >> resulting sid is same. >> Let me explain more. >> >> From sid sheet, >> Description SID (hex) MASK RESULT_SID S1 CB >> CE descriptors 0x84, 0x85 0x11 0x0084 S1_CRYPTO_KERNEL >> (for data pipe 4/5) >> CE descriptors 0x86, 0x87 0x11 0x0086 S1_CRYPTO_USER >> (for data pipe 6/7) >> CE data pipe 4/5 0x94, 0x95 0x11 0x84(same) S1_CRYPTO_KERNEL >> CE data pipe 6/7 0x96, 0x97 0x11 0x86(same) S1_CRYPTO_USER >> >> Qualcomm BAM DMA engine driving QCE has 2 major components here: >> * Descriptor pipe (0x84/0x86): This carries BAM command descriptors i,e >> key, algorithm, length etc. which tell crypto engine what to do. >> * Data pipe (0x94/0x96): This carries the actual data payload — the >> plaintext/ciphertext buffers being read/written. >> >> The descriptor(SID 0x84) basically contain IOVA address that points to >> the data buffer. That same IOVA address is then used by the data pipe >> (SID 0x94) to actually DMA the data. >> >> Since, Crypto engine descriptor and crypto engine data are part of same >> crypto operation and with the limited number of context banks, smmu >> provides an optimization to logically group and resolve them to same >> context bank/page tables. >> >> Pipe 4/5 contain 2 SID(0x84/0x94) for kernel and pipe 6/7 contain >> sid(0x86/0x96) for user. Pipe 4/5 doesn't touch pipe6/7 buffers so both >> are safe. > > I understand they are different from the hardware perspective. Are they > different as far as the OS is concerned? Will we ever need to separate > their data flows? (I guess that would require iommu-maps anyway since > currently they are bound to the same domain anyway) > > Alternatively, if you'd like to keep this level of description, it would > be good to describe the iommus:items: in dt-bindings, so that one can > make sense out of it Ok sure, I'll update iommus:bindings in that case. Please note, I sent v2 and will incorporate in v3. https://lore.kernel.org/lkml/20260702-b4-shikra_crypto_changse-v2-0-66173f2f28b3@qti.qualcomm.com/ -- Regards Kuldeep