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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf9bc214sm1602419566b.52.2025.11.12.01.15.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Nov 2025 01:15:42 -0800 (PST) Message-ID: <66b634ef-6a69-4275-b28d-2b148df22b24@oss.qualcomm.com> Date: Wed, 12 Nov 2025 10:15:39 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1 on monaco-evk To: Sushrut Shree Trivedi , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ziyue.zhang@oss.qualcomm.com, krishna.chundru@oss.qualcomm.com References: <20251111-monaco-evk-pci-v1-1-8013d0d6a7ca@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20251111-monaco-evk-pci-v1-1-8013d0d6a7ca@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: hD6NKwWA7zWC63uRTG9XaAKp2n2mLa1D X-Authority-Analysis: v=2.4 cv=DYwaa/tW c=1 sm=1 tr=0 ts=69145040 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=9FffyO56NNMGgoAXEYMA:9 a=QEXdDO2ut3YA:10 a=zZCYzV9kfG8A:10 a=uxP6HrT_eTzRwkO_Te1X:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: hD6NKwWA7zWC63uRTG9XaAKp2n2mLa1D X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEyMDA3MyBTYWx0ZWRfX3TvkTQQZryPb 38UyzMl/IItv4c8DE48/9Fcgr2xBrYAFCN+uAtGhJC/uPmvP0oeg0QkU2I5mGE/eq+04j17h8LI XKNRmsB1Lcpdihnlk2wdteKNKjXWshGjhxTOePGz+N9zCs22+L0KIdAPBRaNh1ui2fuh7FQ932V dmf+KrZRcZ2Ls2qBJ5OA/0wNcKSYJGAGic4OJM2xy0xFWJBt3DCoYO5+qVOv/Etbqb0kqIl3LJw KpTOVovcdh0EBqnwN5B2fIer3INyo+O6fDAJHqXyDAHH4+gAdLPXh2plTkcfJZf00ogBW1zBPk+ J2UfZrgwlZIbrrJ/9VTovr36RsUg+sX+CZJZrmPev1MlE4Nq3OxmpYSF/d+kLHZjuXGWekPUsTY q/kek33W9CLAKFBkv6YUr8xl+X0UtQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-12_03,2025-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511120073 On 11/11/25 11:08 AM, Sushrut Shree Trivedi wrote: > Enables PCIe0 and PCIe1 controller and phy-nodes. > > PCIe0 is routed to an m.2 E key connector on the mainboard for wifi > attaches while PCIe1 routes to a standard PCIe x4 expansion slot. > > Signed-off-by: Sushrut Shree Trivedi > --- > This patch depends on the series: > https://lore.kernel.org/all/20251024095609.48096-1-ziyue.zhang@oss.qualcomm.com/ > --- [...] > + perst-pins { > + pins = "gpio2"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-down; > + }; Neither of the two active-low reset pins should be pull-down, use bias-disable to avoid spurious assertions Konrad