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Thu, 26 Mar 2026 07:57:38 -0700 (PDT) X-Received: by 2002:a17:90a:d408:b0:35b:a8cf:7969 with SMTP id 98e67ed59e1d1-35c0dd0d076mr6948750a91.11.1774537057676; Thu, 26 Mar 2026 07:57:37 -0700 (PDT) Received: from [10.91.121.222] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35c22cebf63sm1853913a91.15.2026.03.26.07.57.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Mar 2026 07:57:37 -0700 (PDT) Message-ID: <66b8deb8-6138-406e-a503-27cbe5dce2cc@oss.qualcomm.com> Date: Thu, 26 Mar 2026 20:27:30 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 02/16] drm/msm/a6xx: Switch to preemption safe AO counter To: Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Antonino Maniscalco , Connor Abbott , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann References: <20260324-a8xx-gpu-batch2-v1-0-fc95b8d9c017@oss.qualcomm.com> <20260324-a8xx-gpu-batch2-v1-2-fc95b8d9c017@oss.qualcomm.com> <4bd0e8fb-a41b-4d56-88d0-c241d6ab431a@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: <4bd0e8fb-a41b-4d56-88d0-c241d6ab431a@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=NOPYOk6g c=1 sm=1 tr=0 ts=69c54963 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=tHuJs617m-YSc7YiAWEA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-ORIG-GUID: Ibqaxue7b9Q0wlpUMsQsaz6Gtt6qsarG X-Proofpoint-GUID: Ibqaxue7b9Q0wlpUMsQsaz6Gtt6qsarG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI2MDEwNSBTYWx0ZWRfXweQFIQYp7xBa kkNi88P3uVr5x0AmoHkFGzPiDTzjaswz1JpqG42q+pR91tO9cbNjdaBGFJPWEbcq6ILIg3TUnQ1 tczFDrGvc415aDkWy2SF107xM1IMeVz9kznV7uo39QF7FQYaLhnS/ChP21jLLAPhFQd6ozJvP8w e95OC0LN9AmOe92QjA/6dK8kgng3H77ZCRX9gA0CHAfPCBf00PkbK96N6hfGMslSAaugNAx5R0B G4WrmUt090UgG+4j49qZdhoAMNAsHk/1L5LvG4xy0cYcZWDT2vxepuwEBu6zZnrT2A+HoaKUze9 Llul5h/30AUq2a1syNt89ipMN94u7XLrd5IZdSARWYML8UVexwKoqWIf7Mqn8j4PS7JZ3DNUcHO RzvefoQeHFwD6yf+nLmhkwseT5Gk11p/QyK7qVLlxQqeLxVeaPKjveog8qMan50Y/s5omEsPgBf FLLz9QM3wvKVlDwatcA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-26_03,2026-03-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 impostorscore=0 malwarescore=0 bulkscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603260105 On 3/26/2026 2:34 PM, Konrad Dybcio wrote: > On 3/25/26 10:46 PM, Akhil P Oommen wrote: >> On 3/24/2026 3:21 PM, Konrad Dybcio wrote: >>> On 3/23/26 9:12 PM, Akhil P Oommen wrote: >>>> CP_ALWAYS_ON_COUNTER is not save-restored during preemption, so it won't >>>> provide accurate data about the 'submit' when preemption is enabled. >>>> Switch to CP_ALWAYS_ON_CONTEXT which is preemption safe. >>>> >>>> Fixes: e7ae83da4a28 ("drm/msm/a6xx: Implement preemption for a7xx targets") >>>> Signed-off-by: Akhil P Oommen >>>> --- >>>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++---- >>>> 1 file changed, 4 insertions(+), 4 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>>> index 14d5b5e266f7..93bf2c40bfb9 100644 >>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>>> @@ -345,7 +345,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) >>>> * GPU registers so we need to add 0x1a800 to the register value on A630 >>>> * to get the right value from PM4. >>>> */ >>>> - get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, >>>> + get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_CONTEXT, >>>> rbmemptr_stats(ring, index, alwayson_start)); >>>> >>>> /* Invalidate CCU depth and color */ >>>> @@ -386,7 +386,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) >>>> >>>> get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), >>>> rbmemptr_stats(ring, index, cpcycles_end)); >>>> - get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, >>>> + get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_CONTEXT, >>>> rbmemptr_stats(ring, index, alwayson_end)); >>>> >>>> /* Write the fence to the scratch register */ >>>> @@ -478,10 +478,10 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) >>>> >>>> if (adreno_is_a8xx(adreno_gpu)) { >>>> rbbm_perfctr_cp0 = REG_A8XX_RBBM_PERFCTR_CP(0); >>>> - cp_always_on_counter = REG_A8XX_CP_ALWAYS_ON_COUNTER; >>>> + cp_always_on_counter = REG_A8XX_CP_ALWAYS_ON_CONTEXT; >>> >>> I'm a little worried about mixing the names here - KGSL uses both of >>> these registers (A6XX_KERNEL_PROFILE vs A6XX_KERNEL_PROFILE_CONTEXT) >>> to track different fields of the struct adreno_drawobj_profile_entry >> >> But this naming aligns with the HW reg spec. So I prefer to use the same. > > To make it clear, my confusion comes from: > > cp_always_on_counter = REG_A8XX_CP_ALWAYS_ON_CONTEXT > ^^^^^^^ vs ^^^^^^^ > > i.e. I'm not saying this is wrong, but rather that the local variable > could be renamed as well, to match > Aah! okay. Ack. :) -Akhil. > Konrad