From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98492C433E1 for ; Fri, 14 Aug 2020 02:34:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7A5E820838 for ; Fri, 14 Aug 2020 02:34:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726669AbgHNCeK (ORCPT ); Thu, 13 Aug 2020 22:34:10 -0400 Received: from mga18.intel.com ([134.134.136.126]:23203 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726570AbgHNCeK (ORCPT ); Thu, 13 Aug 2020 22:34:10 -0400 IronPort-SDR: s9edopWJtEwbSWPxKhescR3UxUeDqtbKe0ArYLuR6gMZvxdiBXsU1iRaS0M3ia12d//dSrvqjj Uf7NJg37+fRw== X-IronPort-AV: E=McAfee;i="6000,8403,9712"; a="141974250" X-IronPort-AV: E=Sophos;i="5.76,310,1592895600"; d="scan'208";a="141974250" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2020 19:34:09 -0700 IronPort-SDR: 4x3/4P/u0xjbCeCodErI8a0w4AFEf7lBlU2baOIMDWcZ5ijkfhArb0MfI1VRiV6EN8ryzIBps4 6Iq/kQAa4FLA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,310,1592895600"; d="scan'208";a="325595790" Received: from cqiang-mobl.ccr.corp.intel.com (HELO [10.238.2.93]) ([10.238.2.93]) by orsmga008.jf.intel.com with ESMTP; 13 Aug 2020 19:34:07 -0700 Subject: Re: [RFC 6/7] KVM: X86: Expose PKS to guest and userspace To: Jim Mattson Cc: Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Joerg Roedel , Xiaoyao Li , kvm list , LKML References: <20200807084841.7112-1-chenyi.qiang@intel.com> <20200807084841.7112-7-chenyi.qiang@intel.com> From: Chenyi Qiang Message-ID: <66cc68ea-a599-ffd5-9fc9-dd9c0749e3c8@intel.com> Date: Fri, 14 Aug 2020 10:33:45 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/14/2020 3:04 AM, Jim Mattson wrote: > On Fri, Aug 7, 2020 at 1:47 AM Chenyi Qiang wrote: >> >> Existence of PKS is enumerated via CPUID.(EAX=7H,ECX=0):ECX[31]. It is >> enabled by setting CR4.PKS when long mode is active. PKS is only >> implemented when EPT is enabled and requires the support of VM_{ENTRY, >> EXIT}_LOAD_IA32_PKRS currently. >> >> Signed-off-by: Chenyi Qiang > >> @@ -967,7 +969,8 @@ int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) >> { >> unsigned long old_cr4 = kvm_read_cr4(vcpu); >> unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | >> - X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; >> + X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE | >> + X86_CR4_PKS; > > This list already seems overly long, but I don't think CR4.PKS belongs > here. In volume 3 of the SDM, section 4.4.1, it says: > > - If PAE paging would be in use following an execution of MOV to CR0 > or MOV to CR4 (see Section 4.1.1) and the instruction is modifying any > of CR0.CD, CR0.NW, CR0.PG, CR4.PAE, CR4.PGE, CR4.PSE, or CR4.SMEP; > then the PDPTEs are loaded from the address in CR3. > > CR4.PKS is not in the list of CR4 bits that result in a PDPTE load. > Since it has no effect on PAE paging, I would be surprised if it did > result in a PDPTE load. > Oh, My mistake. >> if (kvm_valid_cr4(vcpu, cr4)) >> return 1; >> @@ -1202,7 +1205,7 @@ static const u32 msrs_to_save_all[] = { >> MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, >> MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, >> MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, >> - MSR_IA32_UMWAIT_CONTROL, >> + MSR_IA32_UMWAIT_CONTROL, MSR_IA32_PKRS, > > Should MSR_IA32_PKRS be added to the switch statement in > kvm_init_msr_list()? Something like... > > case MSR_IA32_PKRS: > if (!kvm_cpu_cap_has(X86_FEATURE_PKRS)) > continue; > break; > Yes, this should be added.