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Wed, 10 Dec 2025 05:36:16 -0600 Received: from [172.24.233.254] (santhoshkumark.dhcp.ti.com [172.24.233.254]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5BABaCCs2893034; Wed, 10 Dec 2025 05:36:12 -0600 Message-ID: <66d40c4c-07d0-4474-a288-ae9945a2b269@ti.com> Date: Wed, 10 Dec 2025 17:06:11 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Santhosh Kumar K Subject: Re: [RFC PATCH 01/10] spi: spi-mem: Introduce support for tuning controller To: Michael Walle , Miquel Raynal CC: Pratyush Yadav , , , , , , , , , , , , References: <20250811193219.731851-1-s-k6@ti.com> <20250811193219.731851-2-s-k6@ti.com> <87seguemzu.fsf@bootlin.com> <87jyz3ao8b.fsf@bootlin.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7B:EE_|SA2PR10MB4556:EE_ X-MS-Office365-Filtering-Correlation-Id: 1b6322bf-b7b9-4eb0-5b8e-08de37e0565b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2025 11:36:19.3565 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b6322bf-b7b9-4eb0-5b8e-08de37e0565b X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR10MB4556 On 03/12/25 19:42, Michael Walle wrote: > On Wed Dec 3, 2025 at 10:50 AM CET, Miquel Raynal wrote: >> >>>>> I think we should start with the requirement to have the pattern flashed >>>>> already and figure out how SPI NOR or SPI NAND can discover that >>>>> (perhaps via NVMEM?). >>> >>> But we should also keep in mind that certain flashes might return >>> tuning data during the dummy cycles. I.e. the PHY might probably be >>> tuned on each read and there is no need for any pre-programmed >>> pattern. >>> >>> I'm not saying it should be implemented, but the current >>> implementation should be that flexible that it will be easy to add >>> that later. >> >> Conceptually, yes, but in practice, I know no controller capable of >> using just a few cycles every transfer to calibrate themselves >> automatically and reaching such an optimized speed state as the cadence >> controller is capable of ATM. > > Then have a look at the flexspi controller. I.e. look at the LS1028A > reference manual "18.5.15.1 Data Learning with Flash providing > preamble bit". The sequence is a follows: > > > > There's an example with the learning pattern as short as 8 bit, or > - I guess - 8 clock cycles. In this case, we can skip calling execute_tuning, since *_exec_op would be able to perform the necessary tuning, right? Regards, Santhosh. > >> Despite the end result being close, I would still consider this other >> way to optimize the I/Os somewhat orthogonal. If someone has some >> knowledge to share about the training patterns sent during the dummy >> cycles, I am all ears though. > > There's also a short chapter about the training. Basically, it will > just compare the read bits with a predefined value (which is max > 32 bit long) of 16 different clock phases. Which one is chosen is > not answered though (ideally it should be the one at the center of > all matching clock phases). > > Now how good that tuning actually is, I don't know. But the > procedure sounds sane. I'm also not sure whether this (any?) tuning > will account for different I/O trace lengths of if it is assumed > that they have to be trace length matched for multi IO flashes. > > -michael