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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Hongliang Yang <hongliang.yang@cixtech.com>
Cc: Vinod Koul <vkoul@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Manivannan Sadhasivam <mani@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Gary Yang <Gary.Yang@cixtech.com>,
	Fugang Duan <fugang.duan@cixtech.com>,
	linux-phy@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	cix-kernel-upstream <cix-kernel-upstream@cixtech.com>
Subject: Re: [PATCH v6 1/3] dt-bindings: phy: Add CIX Sky1 USB3 PHY
Date: Wed, 11 Nov 2026 08:52:13 +0100	[thread overview]
Message-ID: <66d48a6d-00c8-42fc-889d-d0901c8d85a6@kernel.org> (raw)
In-Reply-To: <20261111030926.2954510-1-hongliang.yang@cixtech.com>

On 11/11/2026 04:09, Hongliang Yang wrote:
>> So previously you had two phys, now you have only one. Confusing. Where
>> did the second phy go?
> 
> The second PHY did not go anywhere. It is the second lane of the same
> block, and it has no resources of its own.
> 
> v5 described one child node per lane:
> 
> 	usb-phy@9210000 {
> 		...
> 		usb-port@0 {
> 			reg = <0>;
> 			#phy-cells = <0>;
> 		};
> 
> 		usb-port@1 {
> 			reg = <1>;
> 			#phy-cells = <0>;
> 		};
> 	};
> 

This clearly shows two phys - each node with cell=0, means each having
one phy. Two nodes, so two phys.


> Those child nodes had no register range, clocks or resets of their own;
> everything they described belongs to the parent. Both lanes are
> programmed through the same register block, with the same clocks and
> resets, and by the same initialization sequence, so a consumer has
> nothing to configure per lane. The two children only mirrored the two
> controllers.
> 
> v6 makes the parent the provider, with #phy-cells = <0>, and both
> controllers reference the same phandle:
> 
> 	usb3_phy4: usb-phy@9210000 {
> 		compatible = "cix,sky1-usb3-phy";
> 		reg = <0x9210000 0x40000>;
> 		clocks = <&scmi_clk CLK_TREE_USB3A_PHY3_GATE>,
> 			 <&scmi_clk CLK_TREE_USB3A_PHY_x2_REF>;
> 		clock-names = "apb", "ref";
> 		resets = <&s5_syscon SKY1_USBPHY_SS_RST_N>,
> 			 <&s5_syscon SKY1_USBPHY_SS_PST_N>;
> 		reset-names = "core", "apb";
> 		#phy-cells = <0>;
> 	};

I saw the code, why are you pasting the same? What happened with the
second phy?


Best regards,
Krzysztof

  reply	other threads:[~2026-11-11  7:52 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-05  1:17 [PATCH v6 0/3] phy: Add CIX Sky1 USB3 PHY support Hongliang Yang (杨宏亮)
2026-11-05  1:17 ` [PATCH v6 1/3] dt-bindings: phy: Add CIX Sky1 USB3 PHY Hongliang Yang (杨宏亮)
2026-11-05 11:52   ` Krzysztof Kozlowski
2026-11-11  3:09     ` Hongliang Yang
2026-11-11  7:52       ` Krzysztof Kozlowski [this message]
2026-11-05  1:18 ` [PATCH v6 2/3] phy: cix: Add CIX Sky1 USB3 PHY driver Hongliang Yang (杨宏亮)
2026-11-05  1:18 ` [PATCH v6 3/3] arm64: dts: cix: Add USB3 PHY nodes for Sky1 Hongliang Yang (杨宏亮)
2026-11-05 11:51 ` [PATCH v6 0/3] phy: Add CIX Sky1 USB3 PHY support Krzysztof Kozlowski
2026-11-11  3:09   ` Hongliang Yang
2026-11-11  7:51     ` Krzysztof Kozlowski

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