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Tue, 22 Oct 2024 01:43:49 +0000 Date: Mon, 21 Oct 2024 18:43:46 -0700 From: Dan Williams To: Terry Bowman , , , , , , , , , , , , , , , , , Subject: Re: [PATCH 0/15] Enable CXL PCIe port protocol error handling and logging Message-ID: <671703521fd1f_2312294e3@dwillia2-xfh.jf.intel.com.notmuch> References: <20241008221657.1130181-1-terry.bowman@amd.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20241008221657.1130181-1-terry.bowman@amd.com> X-ClientProxiedBy: MW4PR04CA0255.namprd04.prod.outlook.com (2603:10b6:303:88::20) To PH8PR11MB8107.namprd11.prod.outlook.com (2603:10b6:510:256::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8107:EE_|DM4PR11MB7303:EE_ X-MS-Office365-Filtering-Correlation-Id: 639a2ee0-3230-49f2-94f9-08dcf23af991 X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|7416014|376014|921020; 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This is using Qemu with a root > port (0c:00.0), upstream switch port (0d:00.0),and downstream switch port > (0e:00.0). > > This was tested using aer-inject updated to support CE and UCE internal > error injection. CXL RAS was set using a test patch (not upstreamed). Thanks for these test outputs! > > Root port UCE: > root@tbowman-cxl:~/aer-inject# ./root-uce-inject.sh > [ 27.318920] pcieport 0000:0c:00.0: aer_inject: Injecting errors 00000000/00400000 into device 0000:0c:00.0 > [ 27.320164] pcieport 0000:0c:00.0: AER: Uncorrectable (Fatal) error message received from 0000:0c:00.0 > [ 27.321518] pcieport 0000:0c:00.0: PCIe Bus Error: severity=Uncorrectable (Fatal), type=Transaction Layer, (Receiver ID) > [ 27.322483] pcieport 0000:0c:00.0: device [8086:7075] error status/mask=00400000/02000000 > [ 27.323243] pcieport 0000:0c:00.0: [22] UncorrIntErr > [ 27.325584] aer_event: 0000:0c:00.0 PCIe Bus Error: severity=Fatal, Uncorrectable Internal Error, TLP Header=Not available It strikes that by this point the code knows that it is a "CXL Bus" error and no longer a "PCIe Bus" error. Given the divergent responses to Fatal errors based on bus I think it would help to clarify that the kernel is panicking due to "CXL Bus", not "PCIe Bus" errors. > [ 27.325584] > [ 27.327171] cxl_port_aer_uncorrectable_error: device=0000:0c:00.0 host=pci0000:0c status: 'Memory Address Parity Error' ...i.e. someone may not notice that this is "cxl" reference in the backtrace.