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(93-34-91-161.ip49.fastwebnet.it. [93.34.91.161]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0a4aadcsm9357173f8f.40.2024.10.23.10.07.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 10:07:12 -0700 (PDT) Message-ID: <67192d40.5d0a0220.33f6c1.23bc@mx.google.com> X-Google-Original-Message-ID: Date: Wed, 23 Oct 2024 19:07:08 +0200 From: Christian Marangi To: Andrew Lunn Cc: Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Matthias Brugger , AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [net-next RFC PATCH v2 3/3] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY References: <20241023161958.12056-1-ansuelsmth@gmail.com> <20241023161958.12056-4-ansuelsmth@gmail.com> <4ad7b2e9-ddf1-4a82-9d60-7afd1856c770@lunn.ch> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4ad7b2e9-ddf1-4a82-9d60-7afd1856c770@lunn.ch> On Wed, Oct 23, 2024 at 07:00:22PM +0200, Andrew Lunn wrote: > > +static int an8855_config_init(struct phy_device *phydev) > > +{ > > + struct air_an8855_priv *priv = phydev->priv; > > + int ret; > > + > > + /* Enable HW auto downshift */ > > + ret = phy_write(phydev, AN8855_PHY_PAGE_CTRL, AN8855_PHY_EXT_PAGE); > > + if (ret) > > + return ret; > > + ret = phy_set_bits(phydev, AN8855_PHY_EXT_REG_14, > > + AN8855_PHY_EN_DOWN_SHFIT); > > + if (ret) > > + return ret; > > + ret = phy_write(phydev, AN8855_PHY_PAGE_CTRL, AN8855_PHY_NORMAL_PAGE); > > + if (ret) > > + return ret; > > There are locking issues here, which is why we have the helpers > phy_select_page() and phy_restore_page(). The air_en8811h.c gets this > right. Ugh didn't think about it... The switch address is shared with the PHY so yes this is a problem. Consider that this page thing comes from my speculation... Not really use if 1f select page... >From what I observed 0x0 PHY page 0x1 this strange EXT 0x4 acess switch register (every PHY can access the switch) > > Is there anything in common with the en8811h? Does it also support > downshift? Can its LED code be used here? > For some reason part of the LED are controlled by the switch and some are by the PHY. I still have to investigate that (not giving priority to it... just on my todo) For downshift as you notice it's a single bit with no count... >From their comments in the original driver it's said "Enable HW autodownshift" Trying to reach them but currently it's all very obscure. -- Ansuel