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Shenoy" , Vincent Guittot , Chen Yu , Juri Lelli , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Hillf Danton , Shrikanth Hegde , Jianyong Wu , Yangyu Chen , Tingyin Duan , Vern Hao , Vern Hao , Len Brown , Aubrey Li , Zhao Liu , Chen Yu , Adam Li , Aaron Lu , Tim Chen , Josh Don , Gavin Guo , Qais Yousef , Libo Chen , linux-kernel@vger.kernel.org, Madadi Vineeth Reddy References: <34817728117f513084f39a99e18ea9a18cbfd3ae.camel@linux.intel.com> Content-Language: en-US From: Madadi Vineeth Reddy In-Reply-To: <34817728117f513084f39a99e18ea9a18cbfd3ae.camel@linux.intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=dvvWylg4 c=1 sm=1 tr=0 ts=69967546 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=QyXUC8HyAAAA:8 a=6JLQv9UL4AW_bNQ1u0sA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-GUID: 2PjADj3AXGXKVHzDsUQykPVFdNVl1-Iu X-Proofpoint-ORIG-GUID: ceUMUy0HR556-YwK6ZnlhPfQj-fRoepw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE5MDAxNyBTYWx0ZWRfXy/1c3D7htMW+ V4YVIJOdcNBR8DO6YeHeIutnUrMzvmlEj+9ZDz8dyE0H2pfDk0m/erzRtTSiOykhlAwfI9Vaty2 4tBiVVk634/8XReGuicR/pVyIHChf+3AxnYJbTvLrpMFGg0++3M2nqgiON6nfeJIMDfJmukXtCw 2n4/DE1557tUH1RNTXnMkm4TgeNxilgkgC4v9gU5Ax2GgqVME1hkdE4XsMgsaraP9+BA2GGDeMc WxCTZx8iCHG5Gkqu+lGLf6Bb9OoMIbRv3KtbJEL3j7GZsKWnmnuDhWiY2q3OvNQVc7AVYj4Xk+Q nzOKAEK0Stdwm1/Dw50J+3g/D/4Xyv2LIvu3THiz82WwwYZP0oIw9t+tvNPuEGgPAXksFXKLdYn WoK7jd3Lc4D0kMs/ooDw/LI4i3/4GQLTdT+ssn1MS4blr0JZTTf2kmoslN6QxyJ41INIQGtDHk3 aOluj4o4fsE37+AjM/Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-18_05,2026-02-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 phishscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602190017 On 19/02/26 03:14, Tim Chen wrote: > On Wed, 2026-02-18 at 23:24 +0530, Madadi Vineeth Reddy wrote: >> On 11/02/26 03:48, Tim Chen wrote: >>> From: Chen Yu >>> >>> > [ .. snip ..] > >>> >>> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c >>> index d1145997b88d..86b6b08e7e1e 100644 >>> --- a/kernel/sched/fair.c >>> +++ b/kernel/sched/fair.c >>> @@ -1223,6 +1223,19 @@ static inline bool valid_llc_buf(struct sched_domain *sd, >>> return valid_llc_id(id); >>> } >>> >>> +static bool exceed_llc_nr(struct mm_struct *mm, int cpu) >>> +{ >>> + int smt_nr = 1; >>> + >>> +#ifdef CONFIG_SCHED_SMT >>> + if (sched_smt_active()) >>> + smt_nr = cpumask_weight(cpu_smt_mask(cpu)); >>> +#endif >>> + >>> + return !fits_capacity((mm->sc_stat.nr_running_avg * smt_nr), >>> + per_cpu(sd_llc_size, cpu)); >> >> >> On Power10/Power11 with SMT4 and LLC size of 4, this check >> effectively disables cache-aware scheduling for any process. > > There are 4 cores per LLC, with 4 SMT per core? In that case, once we have more than > 4 running threads and there's another idle LLC available, seems > like putting the additional thread on a different LLC is the > right thing to do as threads sharing a core will usually be much > slower. > > But when number of threads are under 4, we should still be > doing aggregation. > > Perhaps I am misunderstanding your topology. There is only one core per LLC whose size is 4 CPUs. So, mm->sc_stat.nr_running_avg can't be >= 1 for cache aware scheduling to be enabled. Thanks, Vineeth > > Tim > >> >> I raised this point in v1 as well. Increasing the threshold >> doesn't seem like a viable solution either, as that would regress >> hackbench/ebizzy. >> >> Is there a way to make this useful for architectures with small LLC >> sizes? One possible approach we were exploring is to have LLC at a >> hemisphere level that comprise multiple SMT4 cores. >> >> Thanks, >> Vineeth