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Content-Language: en-US To: Kenneth Sloat , "sean.anderson@seco.com" , "michal.simek@xilinx.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" References: From: Michal Simek In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT065:EE_|CY5PR12MB6228:EE_ X-MS-Office365-Filtering-Correlation-Id: 30613cae-e835-47f5-3657-08dade954dcd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GdSLZwoXi4DZCGgKGkNwC3NHLROCS1EN94MU/ZxUh8dpbt7mSgjidxCtjJCVJAv1oQco4mIM5KH+P6iQIk3i81EoHXHrWKtuqDcxzZErLpita8WWIl3PICGiYOM1yMPkLvs0rybhNoPdspPcbUHVT3uqyJh21TWq3mBV7G2kKYPNaZUSEclZDBSY5AwHGXZxuNbBrKHA1rzNCjwmF8avtQPnMDaRdq7LTGr9VAtyLnFN8ClON30ilyFhlbY+4Ohk6XAq0wfpfUn3DqGra5VHBunzwVXwXZxMZ5YvU+m6fvD8aO08wRh+9vdOCF1WlgcUvfxpAWWSkK0uRfkeRU691KxcXcKJVGhflgscRkoJ8Vk2GS0c/V5v2kKmPT3RSzfufRBBZtsB29EUwPsiiiCJcdbIMbB0n45TQ8iz7C0KiPIpq3tKMEGq0h7Z3HE0h9v6RwljUIlinZURVF0JV05C4QFrgs4zBsuWLvC/vCXvy0B+3mskuyUdE0SB7OwCkWT3m5u0PVWgzPLZyGsTdmgwzAUEdOUm6B9LaSpKlZ1kafpMv92ZhBd8wLqOqRw+ygEv8Dp4H3VbSnjfuNYnY5BDFa9ADJMJFY01nS4g4jKzulNw7RyM/sHMEAmil18ztO2MI6mRqVw5JCu7EOgJ0gm6ZCDPvJj1XuW96IOQCqCIK5duMh5c9I/JH0Qn/0WiFgqkkWxPIQ1om/g3LA6v8HGvc1c7kC872XwM2Fh3dhrdQYu/eiOqoOVi0H2YdrgqPF08y1K/24MyIdJShN03uF/5ug== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:CA;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(346002)(136003)(396003)(451199015)(46966006)(40470700004)(36840700001)(82740400003)(44832011)(478600001)(81166007)(2906002)(83380400001)(336012)(356005)(2616005)(36860700001)(40460700003)(82310400005)(53546011)(36756003)(186003)(6666004)(16526019)(426003)(47076005)(26005)(70586007)(31696002)(8936002)(40480700001)(41300700001)(31686004)(110136005)(70206006)(8676002)(5660300002)(16576012)(86362001)(316002)(43740500002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2022 12:10:06.2665 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 30613cae-e835-47f5-3657-08dade954dcd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6228 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/12/22 14:59, Kenneth Sloat wrote: > This timer HW supports 8, 16 and 32-bit timer widths. This > driver uses a u32 to store the max value of the timer. > Because addition is done to this max value, when operating > in 32-bit mode, this will result in overflow that makes it > impossible to set the timer period and thus the PWM itself. > > To fix this, simply make max a u64. This was tested on a > Zynq UltraScale+. Can you please be more accurate where that overflow is happening. I see that value is set only at probe like priv->max = BIT_ULL(width) - 1; No doubt that there are calculation based on u64 types. > > Signed-off-by: Ken Sloat > --- > include/clocksource/timer-xilinx.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/clocksource/timer-xilinx.h b/include/clocksource/timer-xilinx.h > index c0f56fe6d22a..d116f18de899 100644 > --- a/include/clocksource/timer-xilinx.h > +++ b/include/clocksource/timer-xilinx.h > @@ -41,7 +41,7 @@ struct regmap; > struct xilinx_timer_priv { > struct regmap *map; > struct clk *clk; > - u32 max; > + u64 max; > }; > > /** > -- > 2.17.1 > Thanks, Michal