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(93-34-91-161.ip49.fastwebnet.it. [93.34.91.161]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38242eef982sm7148949f8f.8.2024.11.19.01.04.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2024 01:04:28 -0800 (PST) Message-ID: <673c549c.5d0a0220.3a3476.517a@mx.google.com> X-Google-Original-Message-ID: Date: Tue, 19 Nov 2024 10:04:27 +0100 From: Christian Marangi To: Viresh Kumar Cc: "Rafael J. Wysocki" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Lorenzo Bianconi , upstream@airoha.com Subject: Re: [PATCH v2] cpufreq: airoha: Add EN7581 Cpufreq SMC driver References: <20241017190809.16942-1-ansuelsmth@gmail.com> <20241119072054.64hi347qmv7ng3un@vireshk-i7> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241119072054.64hi347qmv7ng3un@vireshk-i7> On Tue, Nov 19, 2024 at 12:50:54PM +0530, Viresh Kumar wrote: > On 17-10-24, 21:07, Christian Marangi wrote: > > Add simple Cpufreq driver for Airoha EN7581 SoC that control CPU > > frequency scaling with SMC APIs. > > > > All CPU share the same frequency and can't be controlled independently. > > Current shared CPU frequency is returned by the related SMC command. > > > > Add SoC compatible to cpufreq-dt-plat block list as a dedicated cpufreq > > driver is needed with OPP v2 nodes declared in DTS. > > > > Signed-off-by: Christian Marangi > > --- > > Changes v2: > > - Fix kernel bot error with missing slab.h and bitfield.h header > > - Limit COMPILE_TEST to ARM64 due to smcc 1.2 > > Hi, > > Sorry for delay at my side to review this driver. > > Now that I looked at it, I don't see a lot of special stuff happening in the > driver. There are many other platforms with similar situation. What we have done > for all them, which rely on OPPs coming from DT, is to add a clk for the CPUs > and do all this magically smcc stuff from clk_get_rate() and clk_set_rate(). > Once that is done, you should be able to reuse the cpufreq-dt driver as is. > > So a CPU clk is the only missing thing in your case I guess. > Hi Viresh, thanks a lot for the follow-up. I will see what I can do, 2 main problem I see is that, contrary to other driver, for this Airoha SoC, there are no parents or no clock to enable... It's really just entirely handled by ATF and smccc call. And also the SMCCC requires an index and not the clock itself. This was handy for a cpufreq driver as it passed the OPP index, problematic for a clock driver as set_rate pass the clock. So I guess I will have to define the OPP phandle also in the clock node struct. (and map it?) The main problem in doing that is the performance hit on having to cycle every time the OPPs to find the correct index... (yes they really implemented this thing with the ATF specifically with the cpufreq scenario in mind) Wonder if you have any hint on any of this. -- Ansuel