Re: [PATCH v3 6/6] iio: adc: xilinx-xadc: Correct Write edge in CFG

[David Lechner <dlechner@baylibre.com>]

On 7/29/26 7:54 AM, Dileep Kumar Nagavarapu wrote:
> UG585 states about the PS-XADC interface configuration steps,
> REDGE is 1 and WEDGE is 0, this is consistent with the XADCIF_CFG
> register default value.
> 
> Current driver set WEDGE which is inconsistent with TRM, this patch
> fix the WEDGE parameter setting.
> 
> Signed-off-by: Conall O'Griofa <conall.ogriofa@amd.com>
> Signed-off-by: Dileep Kumar Nagavarapu <DileepKumar.Nagavarapu@amd.com>
> ---
>  drivers/iio/adc/xilinx-xadc-platform.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/iio/adc/xilinx-xadc-platform.c b/drivers/iio/adc/xilinx-xadc-platform.c
> index bd033315c72f..b113f904b8fa 100644
> --- a/drivers/iio/adc/xilinx-xadc-platform.c
> +++ b/drivers/iio/adc/xilinx-xadc-platform.c
> @@ -346,7 +346,7 @@ static int xadc_zynq_setup(struct platform_device *pdev, struct iio_dev *indio_d
>  	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
>  	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
>  	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE | XADC_ZYNQ_CFG_REDGE |
> -			       XADC_ZYNQ_CFG_WEDGE | tck_div | XADC_ZYNQ_CFG_IGAP(igap));
> +			       tck_div | XADC_ZYNQ_CFG_IGAP(igap));
>  
>  	if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX_HZ) {
>  		ret = clk_set_rate(xadc->clk, pcap_rate);

This sounds like a fix, so should have Fixes: tag and be the first
patch in the series.

Also would be good to know if this is causing actual problems or
not so we know if it needs to be backported or not.