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From: Antonio Quartulli <antonio@mandelbit.com>
To: Dragos Tatulea <dtatulea@nvidia.com>, netdev@vger.kernel.org
Cc: saeedm@nvidia.com, tariqt@nvidia.com, mbloch@nvidia.com,
	leon@kernel.org, cratiu@nvidia.com, andrew+netdev@lunn.ch,
	davem@davemloft.net, edumazet@kernel.org, kuba@kernel.org,
	pabeni@redhat.com, ast@kernel.org, daniel@iogearbox.net,
	hawk@kernel.org, john.fastabend@gmail.com, sdf@fomichev.me,
	linux-rdma@vger.kernel.org, bpf@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH net-next v2] net/mlx5e: Prefetch the packet a few strides ahead in the linear MPWQE path
Date: Tue, 10 Nov 2026 11:40:49 +0100	[thread overview]
Message-ID: <674eb8ef-c93f-4926-a760-62df154ed3eb@mandelbit.com> (raw)
In-Reply-To: <a31e1e60-7e31-4a14-a087-428d1e3627f2@nvidia.com>

Hi Dragos,

On 06/11/2026 11:55, Dragos Tatulea wrote:
> Thanks for your patch! These look indeed like enticing numbers. I'd
> like to take some time to try this at scale and on other NICs (CX8)
> and CPUs (Grace) and also check latency.

Thanks! In case it helps, I measured latency on my side in the meantime
(I don't have access to the monster Grace/CX8 equipment, but it's still
something :-)).

Request/response over the bare ports (one transaction in flight, like
netperf UDP_RR/TCP_RR), same system as in the commit message: one RX
queue per port with its IRQ on a dedicated CPU, MTU 1500, default
coalescing (adaptive RX, rx-usecs 8, rx-frames 128), 10s per test,
prefetch off / v2 / v2 + next-WQE follow-up (see below) interleaved,
mean of 3 rounds:

                      p50 (us)              p90 (us)
                  off    v2    +next    off    v2    +next
   UDP, 64 B     24.60  24.61  24.60   25.37  25.37  25.39
   UDP, 1400 B   25.08  25.08  25.10   25.94  25.96  25.92
   TCP, 64 B     24.65  24.64  24.66   25.48  25.46  25.85 (*)

   (*) one round at 26.59, the other two at 25.47 and 25.50

p99 and p99.9 (37-45 us and 67-100 us) varied more between rounds than
between the variants, and nothing was lost. So no latency cost that I
could see at low rate.

I'm also testing a small follow-up: v2 doesn't prefetch when the stride
4 ahead is in the next WQE, so the first strides of every WQE are never
prefetched. Following the WQ list to the next WQE (only when
cur_sz >= 2, so it is posted and its pages are allocated) removes 26-32%
of the remaining DRAM demand fills on the RX CPU and adds 1.8-3.3%
throughput, measured with TCP inside an ovpn UDP tunnel (where the RX
CPU is the bottleneck); its latency is the "+next" column above.

I had planned to send it as a follow-up patch, but I can also fold it in 
a v3, whatever you prefer once you have your results.

If there is anything specific you'd like me to run here, feel free
to let me know.


Thanks!


-- 
Antonio Quartulli

CEO and Co-Founder
Mandelbit Srl
https://www.mandelbit.com


      reply	other threads:[~2026-11-10 10:41 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-04 19:52 Antonio Quartulli
2026-11-06 10:55 ` Dragos Tatulea
2026-11-10 10:40   ` Antonio Quartulli [this message]

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