Re: [PATCH 2/3] Documentation: sysfs: brcmstb-memc: Document new attributes

[Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]

On 24/03/2023 17:52, Florian Fainelli wrote:
> Document the DDR rank, size, total size, width and type attributes.
> 
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  .../ABI/testing/sysfs-platform-brcmstb-memc   | 39 +++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/Documentation/ABI/testing/sysfs-platform-brcmstb-memc b/Documentation/ABI/testing/sysfs-platform-brcmstb-memc
> index 2f2b750ac2fd..bc969c02b85f 100644
> --- a/Documentation/ABI/testing/sysfs-platform-brcmstb-memc
> +++ b/Documentation/ABI/testing/sysfs-platform-brcmstb-memc
> @@ -1,3 +1,42 @@
> +What:		/sys/bus/platform/devices/*/ddr_rank
> +Date:		March 2023
> +KernelVersion:	6.3

We are now at v6.3, so this cannot go into current cycle. Date is also
not realistic. Target v6.4 and it's date from the crystal ball.

> +Contact:	Florian Fainelli <f.fainelli@gmail.com>
> +Description:
> +		Displays whether the device is single or dual rank.
> +
> +What:		/sys/bus/platform/devices/*/ddr_size
> +Date:		March 2023
> +KernelVersion:	6.3
> +Contact:	Florian Fainelli <f.fainelli@gmail.com>
> +Description:
> +		This field specifies the size of each DRAM device in the first
> +		(or only) rank

Why only first rank? Have in mind that one physical chip can have
multiple ranks and the interface should be ready for it. Otherwise soon
you will have to break it to support different sizes in different ranks.

> +
> +What:		/sys/bus/platform/devices/*/ddr_total_width
> +Date:		March 2023
> +KernelVersion:	6.3
> +Contact:	Florian Fainelli <f.fainelli@gmail.com>
> +Description:
> +		This field specifies the total data width of all DRAM devices
> +		(in each rank)

Sorry, I do not understand. "Total" and "in each" are a bit
contradictory. Also misses units description. Is this

> +
> +What:		/sys/bus/platform/devices/*/ddr_type
> +Date:		March 2023
> +KernelVersion:	6.3
> +Contact:	Florian Fainelli <f.fainelli@gmail.com>
> +Description:
> +		This field specifies DRAM technology type. Possible values:
> +		DDR2, DDR3, DDR4, GDDR5, GDDR5M, LPDDR4.
> +
> +What:		/sys/bus/platform/devices/*/ddr_width
> +Date:		March 2023
> +KernelVersion:	6.3
> +Contact:	Florian Fainelli <f.fainelli@gmail.com>
> +Description:
> +		This field specifies the data width of each DRAM device.

Width in which units? And width of what exactly? data-bus? Then bits and
make it maybe "ddr_width_bits" and print 8/16/32. Is it IO width (number
of DQ pins)? Then it could be also up to 128 in general.


Best regards,
Krzysztof