From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m1973186.qiye.163.com (mail-m1973186.qiye.163.com [220.197.31.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3AC0339714 for ; Thu, 23 Jul 2026 13:05:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.86 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784811923; cv=none; b=pV7IBF28IUzmSWMyAXn5NxKWN80iRcJIVrwU1rW6VIyIogaONM3VDav5gfNt5xJSqUlsbjvPQe6GakWofKrJ8/DX4P0t7eZAZDPNIZ+8rjLf8GKk4/7qfNiYKR0IcjmHot5Q0QLgQaAfVhBjHQ0PLR/wrrG3I6wzxsKs/DjHP8E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784811923; c=relaxed/simple; bh=GUcRq80HbAUT1WrGJ4IaO3LSIWBdX7IGBDfTgclUyXU=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=SpBwo8Zib6ABj30a5MfAsiYc7mXiORk6vjIFOqhi58pJTfCCY+RxW6xWxFVva76an84OGxFyVJ90uerURkinJCuddnY4wxrf3Hicnzlu8BBXVgRqS+PjVg45niI88ImK+1Xpf9l6lhw4D9xQspJN2f7oNSWm0kJy0163eOjwRIU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=X7Xqdg4Z; arc=none smtp.client-ip=220.197.31.86 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="X7Xqdg4Z" Received: from [172.16.12.77] (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 475247b2e; Thu, 23 Jul 2026 19:49:32 +0800 (GMT+08:00) Message-ID: <676d0baa-98c9-417d-91b0-0a9cc07d464c@rock-chips.com> Date: Thu, 23 Jul 2026 19:49:31 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/8] phy: rockchip: samsung-hdptx: Prevent divide-by-zero when computing clk rate To: Cristian Ciocaltea , Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Sashiko References: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> <20260612-hdptx-clk-fixes-v4-2-ce5e1d456cda@collabora.com> Content-Language: en-US From: Andy Yan In-Reply-To: <20260612-hdptx-clk-fixes-v4-2-ce5e1d456cda@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-HM-Tid: 0a9f8ecf362e09d8kunm45c8aff254ee X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1kYFggdWUFKV1ktWUFJV1kPCRoVCBIfWUFZQklCSlZCQ0wYGhlNQ0 0aHU9WFRQJFhoXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0 tIVUpLSEpKQkxVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=X7Xqdg4Z42g/5lfR4vXGT5Dsyta9ef9az6uvuMhqlSEQbK3gTo1+h3I4zkrT+oqH6A46NcXhx6IGPAMp0R3oum5vMv0bsX9+Jxsbg8Qx5quN6KWZoihEf98kRiqvNb3dxk4GeKR91yzYKLZa/4XQBp0U1Kx9KWDpGMfOhyOCMHE=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=L1A7SLzIpbSpqM14bWF0t1CZA/db+dQzBITowvt1p1c=; h=date:mime-version:subject:message-id:from; Hello, On 6/12/26 07:45, Cristian Ciocaltea wrote: > Calculating 'sdm' fraction in rk_hdptx_phy_clk_calc_rate_from_pll_cfg() > could trigger a divide-by-zero, as it uses div_u64() with a denominator > read directly from hardware: the values ropll_hw.sdm_deno, > ropll_hw.sdc_deno, ropll_hw.sdc_n, and ropll_hw.sdc_num are populated > from PLL registers which, in theory, could be left by the bootloader > uninitialized/misconfigured. > > Provide the necessary sanitization to avoid trusting the hardware state. > > Reported-by: Sashiko > Closes: https://sashiko.dev/#/patchset/20260611-hdptx-clk-fixes-v3-0-67b1b0c00e16@collabora.com?part=1 > Fixes: 3481fc04d969 ("phy: rockchip: samsung-hdptx: Compute clk rate from PLL config") > Signed-off-by: Cristian Ciocaltea Reviewed-by: Andy Yan > --- > drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > index 710603afff86..8c044381b83a 100644 > --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > @@ -2270,10 +2270,15 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(struct rk_hdptx_phy *hdptx) > > fout = PLL_REF_CLK * ropll_hw.pms_mdiv; > if (ropll_hw.sdm_en) { > + val = 16U * ropll_hw.sdm_deno * > + (ropll_hw.sdc_deno * ropll_hw.sdc_n - ropll_hw.sdc_num); > + if (!val) { > + dev_dbg(hdptx->dev, "%s invalid ROPLL hw state\n", __func__); > + return 0; > + } > + > sdm = div_u64(PLL_REF_CLK * ropll_hw.sdc_deno * > - ropll_hw.pms_mdiv * ropll_hw.sdm_num, > - 16 * ropll_hw.sdm_deno * > - (ropll_hw.sdc_deno * ropll_hw.sdc_n - ropll_hw.sdc_num)); > + ropll_hw.pms_mdiv * ropll_hw.sdm_num, val); > > if (ropll_hw.sdm_num_sign) > fout = fout - sdm; >