From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751536AbdFHTBO (ORCPT ); Thu, 8 Jun 2017 15:01:14 -0400 Received: from smtprelay4.synopsys.com ([198.182.47.9]:58876 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751505AbdFHTBN (ORCPT ); Thu, 8 Jun 2017 15:01:13 -0400 Subject: Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception To: Noam Camus CC: "linux-snps-arc@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Elad Kanfi References: <1495954328-28736-1-git-send-email-noamca@mellanox.com> <1495954328-28736-12-git-send-email-noamca@mellanox.com> <15ef64f3-3b5b-a362-c520-e5316121d3d6@synopsys.com> From: Vineet Gupta Message-ID: <67715c5d-30f2-815e-87ab-7fb4e8205a90@synopsys.com> Date: Thu, 8 Jun 2017 12:00:38 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-Originating-IP: [10.10.161.108] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/08/2017 11:23 AM, Noam Camus wrote: > > > *> From:* Vineet Gupta > *> Sent:* Thursday, June 8, 2017 7:38 PM > > >> > >> With simulator we just turn this configuration on, so we redirect the Legacy > >> Synopsys L2 ISR from nSIM into machine check. > >> This way we end up just like with silicon 😊 > > >This doesn't make sense :-) > >In simulation (where L2 interrupt is asserted), you need to handle it as such - > >say reading out the banked regs for L2 interrupt. What you are doing here is > >handling it like an exception which won't work . I really don't see the point of > >this "alignment" - hardware and simulation are different. simulation semantics are > >already supported by generic ARC code. And for silicon case, the existing vector > >woudl MachineCheck would work for both K and U. So I'm not sure what we are trying > >to achieve here ! > With EZsim we try to simulate NPS400 CTOP core and not ARC core, and as such we > strive to have similar echo system for both silicon and its simulator. Right, but if you are using nSIM which generates L2 interrupt for user mode error - then it is already different from silicon and needs to handled as such. > If we could, we would alter nSIM to behave just like our silicon. > So in current situation where we lack doing so we suffice in single pretty small > adjustment in OS (platform specific code). You are saying contradicting things here. Above u want EZSim to simulate CTOP (i.e. generate machinechk for U errors) but here you claim u use nSIM which will generates L2 intr. So I'm still grossly confused. What does EZSim (based on nSIM) do when bus error is triggered from User mode - does it raise (A) L2 interrupt or (B) MachineCheck ? If it is (A) the the existing common code in ARC will work - mem_service() -> do_memory_error() -> panic() if it is (B), again the common machinecheck handler will be called and will panic. I don't see the need to mix both (A) and (B) i.e. use mem_service() which is a L2 interrupt, but then handle it in MachieChekc which is for exceptions ? How is that supposed to work ! -Vineet