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Fri, 06 Mar 2026 01:40:08 -0800 (PST) X-Received: by 2002:a17:903:3bac:b0:2ae:4ac7:bcb9 with SMTP id d9443c01a7336-2ae75b49d80mr47915845ad.9.1772790007870; Fri, 06 Mar 2026 01:40:07 -0800 (PST) Received: from [192.168.1.11] ([106.222.228.80]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ae83f752bfsm19179615ad.60.2026.03.06.01.40.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Mar 2026 01:40:07 -0800 (PST) Message-ID: <67922413-af8d-4e75-aa49-079889576a73@oss.qualcomm.com> Date: Fri, 6 Mar 2026 15:10:01 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes To: Taniya Das Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Abel Vesa , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio References: <20260305-gpucc_sm8750_v2-v5-0-78292b40b053@oss.qualcomm.com> <20260305-gpucc_sm8750_v2-v5-3-78292b40b053@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: <20260305-gpucc_sm8750_v2-v5-3-78292b40b053@oss.qualcomm.com> Content-Type: text/plain; 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The GPU itself > needs some more work and will be enabled later. > > Reviewed-by: Abel Vesa > Signed-off-by: Konrad Dybcio > Co-developed-by: Taniya Das > Signed-off-by: Taniya Das > --- > arch/arm64/boot/dts/qcom/sm8750.dtsi | 68 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 68 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi > index f56b1f889b857a28859910f5c4465c8ce3473b00..0e7a343297e3f5d7a8189f50726dc6279078c21c 100644 > --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi > @@ -4,7 +4,9 @@ > */ > > #include > +#include > #include > +#include > #include > #include > #include > @@ -3001,6 +3003,34 @@ videocc: clock-controller@aaf0000 { > #power-domain-cells = <1>; > }; > > + gxclkctl: clock-controller@3d64000 { > + compatible = "qcom,sm8750-gxclkctl"; > + reg = <0x0 0x03d64000 0x0 0x6000>; > + > + power-domains = <&rpmhpd RPMHPD_GFX>, > + <&rpmhpd RPMHPD_GMXC>, > + <&gpucc GPU_CC_CX_GDSC>; > + > + #power-domain-cells = <1>; > + }; > + > + gpucc: clock-controller@3d90000 { > + compatible = "qcom,sm8750-gpucc"; > + reg = <0x0 0x03d90000 0x0 0x9800>; > + > + clocks = <&bi_tcxo_div2>, > + <&gcc GCC_GPU_GPLL0_CLK_SRC>, > + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; > + > + power-domains = <&rpmhpd RPMHPD_MX>, > + <&rpmhpd RPMHPD_CX>; > + required-opps = <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > pdc: interrupt-controller@b220000 { > compatible = "qcom,sm8750-pdc", "qcom,pdc"; > reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; > @@ -4515,6 +4545,44 @@ tpdm_swao_out: endpoint { > }; > }; > > + adreno_smmu: iommu@3da0000 { Should we move this node right after the gpucc node to sort based on address? -Akhil. > + compatible = "qcom,sm8750-smmu-500", "qcom,adreno-smmu", > + "qcom,smmu-500", "arm,mmu-500"; > + reg = <0x0 0x03da0000 0x0 0x40000>; > + #iommu-cells = <2>; > + #global-interrupts = <1>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; > + clock-names = "hlos"; > + power-domains = <&gpucc GPU_CC_CX_GDSC>; > + dma-coherent; > + }; > + > apps_smmu: iommu@15000000 { > compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > reg = <0x0 0x15000000 0x0 0x100000>; >