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Tue, 20 Oct 2026 22:25:50 -0700 (PDT) Received: from [10.253.160.36] ([106.192.14.26]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36741e71eaesm7184384eec.26.2026.10.20.22.25.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 20 Oct 2026 22:25:49 -0700 (PDT) Message-ID: <679f383a-97a1-4505-8bd9-73ef76bc0d87@oss.qualcomm.com> Date: Wed, 21 Oct 2026 10:55:42 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] ASoC: qcom: sc8280xp: Derive TDM channels from DT mask To: Shawn Guo , Mark Brown Cc: Srinivas Kandagatla , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Zhangfei Gao , Bartosz Golaszewski , linux-sound@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261021025310.2072026-1-shengchao.guo@oss.qualcomm.com> Content-Language: en-US From: Mohammad Rafi Shaik In-Reply-To: <20261021025310.2072026-1-shengchao.guo@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=aI5lOr9m c=1 sm=1 tr=0 ts=6ad84ce0 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=IUwO3uqH19SZaseHF7nCgw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=iFd55WBnZZna6GIBd50A:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-ORIG-GUID: IJR35ZreeBuoW3QnCgPS6xSnfIH6bIOD X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDAyMSBTYWx0ZWRfX2lrUnj8nm+mt VvtcLv7+dLwhLeTQ4wp8yhkPAWSPBIH1EioFzLKnu9PXYFHJTflUujZgNSihrnoN6S7kK1kjCfp iuqxmgDUVf67MZz3tTPao2cututdQjMi6NJ7oCio0lY7h0CCoI28MTvXBAR4+ODZHlnrdGykRwv QeG6b7sCFKGqUttk1rmCSXW+t7g5YAMYXvM2PhZ6pn2xeXTuHFDGSgvJyzA0L+ec+diVkeZV/um k/TerJyPbg0HA1wFR7S4+ZlXjGp6UPnwLsw03TI49kUTDeH05ExvaEu330NssVRzf8XieoI3DRu HJPiR/LP9ZoFO/ZV7XvglEvk83JepRyja2q2NoQE8PIQqFD+5VyGNUai1ff9X70Z456FN9JAJS2 IoEJOYgQ6pqeGNLoWIP9Xraln1n271xxTWOE4pgFyHiq7fahVioHwbtWI33PLslP1fRDCEyVom7 NqXKKrbcQEQ5pb4bG6w== X-Proofpoint-GUID: IJR35ZreeBuoW3QnCgPS6xSnfIH6bIOD X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDAyMSBTYWx0ZWRfX1LBJAS3qbZR5 c5aDGffHOrm4Y6CxUq4m7+ZReep4yFFkNFxQ4Q8xrMEhmNEfCmLeBXPld0h6cOW2Yr2jzkx9CUY AQYUNck3Af0R37MU11j88BQrOdUXKe4= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-21_01,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 bulkscore=0 malwarescore=0 suspectscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210021 On 10/21/2026 8:23 AM, Shawn Guo wrote: > Derive the AIF_TDM_RX_8 and AIF_TDM_TX_8 backend channel count from > the cpu DAI TDM slot mask in the DT, using the same tx/rx mask > selection as q6tdm_set_tdm_slot(). Each board then gets the channel > count its dai-link describes, e.g. 4/4 on Nord RRD, 6/4 on RIDE. > Keep the default of two when the link has no TDM slot description. > > Signed-off-by: Shawn Guo > --- > sound/soc/qcom/sc8280xp.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/sound/soc/qcom/sc8280xp.c b/sound/soc/qcom/sc8280xp.c > index 9aae6aadd43d..f3fb13145b3b 100644 > --- a/sound/soc/qcom/sc8280xp.c > +++ b/sound/soc/qcom/sc8280xp.c > @@ -303,6 +303,22 @@ static int sc8280xp_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, > channels->min = 2; > channels->max = 2; > switch (cpu_dai->id) { > + case AIF_TDM_RX_8: > + case AIF_TDM_TX_8: { This should not be limited to AIF_TDM_RX_8/AIF_TDM_TX_8. Enable it for all TDM DAI IDs. case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7: case AIF_TDM_RX_0 ... AIF_TDM_TX_12: Best Regards, Rafi > + struct qcom_snd_tdm_slot_cfg cpu_cfg, codec_cfg; > + unsigned int mask; > + > + if (qcom_snd_get_dai_tdm_slots(rtd, &cpu_cfg, &codec_cfg)) > + break; > + > + /* Same slot mask selection as q6tdm_set_tdm_slot() */ > + mask = (cpu_dai->id & 0x1) ? cpu_cfg.tx_mask : cpu_cfg.rx_mask; > + if (mask) { > + channels->min = hweight32(mask); > + channels->max = channels->min; > + } > + break; > + } > case TX_CODEC_DMA_TX_0: > case TX_CODEC_DMA_TX_1: > case TX_CODEC_DMA_TX_2: