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Mon, 09 Nov 2026 20:24:25 -0800 (PST) Received: from cantal.lan ([58.136.75.91]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3751fe32276sm3116950eec.8.2026.11.09.20.24.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 20:24:24 -0800 (PST) From: James Clark To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones Cc: Siddharth Vadapalli , Roger Quadros , Sebastian Andrzej Siewior , Martin Kaistra , Vadim Fedorenko , Rahul Sharma , Robert Nelson , Nishanth Menon , Vignesh Raghavendra , Chintan Vankar , netdev@vger.kernel.org, devicetree@vger.kernel.org, mfd@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next 2/3] dt-bindings: net: ti,k3-am654-cpts: add ti,gtc-push Date: Tue, 10 Nov 2026 11:24:02 +0700 Message-ID: <680b4e98af630c4759dbdf73b53926ec5f87fc3b.1794284248.git.jjc@jclark.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: References: X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Global Timebase Counter (GTC) of TI K3 SoCs is the system counter, the one the Arm cores read as the architected counter. It can export one of its counter bits, selected by GTC_CFG0_PUSHEVT, as a push event output, and the Time Sync Router can route that output to one of the CPTS hardware timestamp push inputs (HWx_TS_PUSH). The CPTS then timestamps edges that fall at known counter values, which gives pairs of CPTS and system counter values. Add an optional ti,gtc-push property giving the GTC CFG0 syscon and the HWx_TS_PUSH input the push event is routed to. The CPTS driver uses this to write GTC_CFG0_PUSHEVT. The router itself is configured separately, as it is for ti,pps. Signed-off-by: James Clark --- .../bindings/net/ti,k3-am654-cpts.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml index 3572749147fb..7bf5bedc2b9c 100644 --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml @@ -101,6 +101,23 @@ properties: The pair of HWx_TS_PUSH input and TS_GENFy output indexes used for PPS events generation. Platform/board specific. + ti,gtc-push: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the Global Timebase Counter (GTC) CFG0 + syscon + - description: HWx_TS_PUSH input index (0-based) the GTC push event + is routed to + maximum: 7 + description: | + The GTC is the SoC's system counter (the Arm architected counter). Its + push event output, one counter bit selected by GTC_CFG0_PUSHEVT, reaches + a CPTS hardware timestamp push input through the Time Sync Router. With + this property the CPTS timestamps that signal to provide hardware + cross-timestamps of the CPTS and the system counter. The router is + configured separately. Platform/board specific. + refclk-mux: type: object additionalProperties: false -- 2.56.0