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Wed, 23 Oct 2024 10:59:39 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 355724002D; Wed, 23 Oct 2024 10:58:30 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 29FBE265534; Wed, 23 Oct 2024 10:57:00 +0200 (CEST) Received: from [192.168.8.15] (10.48.87.33) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Wed, 23 Oct 2024 10:56:59 +0200 Message-ID: <680f3e0b7458015d5b909200342a623eb55f907d.camel@foss.st.com> Subject: Re: [PATCH 04/14] dt-bindings: pinctrl: stm32: add RSVD mux function From: Antonio Borneo To: Krzysztof Kozlowski CC: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , , , , , =?ISO-8859-1?Q?Cl=E9ment?= Le Goffic , Stephane Danieau , Amelie Delaunay , Fabien Dessenne , Valentin Caron , Gatien Chevallier , Cheick Traore , Date: Wed, 23 Oct 2024 10:56:57 +0200 In-Reply-To: References: <20241022155658.1647350-1-antonio.borneo@foss.st.com> <20241022155658.1647350-5-antonio.borneo@foss.st.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.48.4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 On Wed, 2024-10-23 at 10:47 +0200, Krzysztof Kozlowski wrote: > On Tue, Oct 22, 2024 at 05:56:48PM +0200, Antonio Borneo wrote: > > From: Fabien Dessenne > >=20 > > Document the RSVD (Reserved) mux function, used to reserve pins > > for a coprocessor not running Linux. > >=20 > > Signed-off-by: Fabien Dessenne > > Signed-off-by: Antonio Borneo > > --- > > =C2=A0.../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml=C2=A0=C2=A0= =C2=A0=C2=A0 | 8 ++++++++ > > =C2=A0include/dt-bindings/pinctrl/stm32-pinfunc.h=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 1 + > > =C2=A02 files changed, 9 insertions(+) > >=20 >=20 > BTW, which *existing* SoCs use it? Aren't you adding it for the new > platform? >=20 This is already used in ST downstream kernel for STM32MP15x In this example https://github.com/STMicroelectronics/linux/blob/v6.1-stm32mp/arch/arm/boot= /dts/stm32mp157f-dk2-m4-examples.dts#L112 the GPIOs for LED and for PWM are assigned to the Cortex-M4 and Linux (on C= ortex-A7) is not supposed to touch them. Regards, Antonio