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From: Matti Linnanvuori <mattilinnanvuori@yahoo.com>
To: linux-kernel@vger.kernel.org
Cc: bugme-daemon@kernel-bugs.osdl.org
Subject: [patch] sync_bitops: fix wrong comments [Bug 10247]
Date: Sun, 16 Mar 2008 02:47:35 -0700 (PDT)	[thread overview]
Message-ID: <681011.80694.qm@web52002.mail.re2.yahoo.com> (raw)

From: Matti Linnanvuori mattilinnanvuori@yahoo.com

Fix wrong function name and references to non-x86 architectures.

Signed-off-by: Matti Linnanvuori mattilinnanvuori@yahoo.com

---

--- a/include/asm-x86/sync_bitops.h 2008-03-16 11:34:59.934699500 +0200
+++ b/include/asm-x86/sync_bitops.h 2008-03-16 11:36:35.866059500 +0200
@@ -23,10 +23,6 @@
  * This function is atomic and may not be reordered.  See __set_bit()
  * if you do not require the atomic guarantees.
  *
- * Note: there are no guarantees that this function will not be reordered
- * on non-x86 architectures, so if you are writing portable code,
- * make sure not to rely on its reordering guarantees.
- *
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
@@ -61,8 +57,7 @@ static inline void sync_clear_bit(int nr
  * @nr: Bit to change
  * @addr: Address to start counting from
  *
- * change_bit() is atomic and may not be reordered. It may be
- * reordered on other architectures than x86.
+ * sync_change_bit() is atomic and may not be reordered.
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
@@ -80,7 +75,6 @@ static inline void sync_change_bit(int n
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
- * It may be reordered on other architectures than x86.
  * It also implies a memory barrier.
  */
 static inline int sync_test_and_set_bit(int nr, volatile unsigned long * addr)
@@ -99,7 +93,6 @@ static inline int sync_test_and_set_bit(
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
- * It can be reorderdered on other architectures other than x86.
  * It also implies a memory barrier.
  */
 static inline int sync_test_and_clear_bit(int nr, volatile unsigned long * addr)


---


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             reply	other threads:[~2008-03-16  9:54 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-03-16  9:47 Matti Linnanvuori [this message]
2008-03-21 11:09 ` Ingo Molnar

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