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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Um/IKVFj53j7O5ZfcgDXl2NK4l/6qmx5M1Wa0L81Am78oVjWKeQ+Q595ePWhKibtBd2N59S75OMR/GgD0/HYUZli8TO9356n8osZDm0JjjW/5KHSSCtB7U2tkrWyQO9fMwgQqxJDPkLy5R83+MrxLEM5AYB1+C/5Z4lvy9/j9mbNY1+5kZ7aE35m/BA/K69JRyqrv1XsoPgjAE1tQVrBIluac3+GVPXSHcDbzjeFQ/TrjlNRBe8Jd3voyT4FeHDRHNpgYISjVzdB5xmiqtSsQixGyqmm3Ce2Znj5n4vi6F+GAsj3UM+3b+/nWFp3r2eTxkVUKMPo2YIy2xs3ZSnedEksdqWWLv9eEnxS2nk3mPRsbEVKoKxeO+9yDjTfQ05MrH/ntN5mFaITO6l9want0asDqh9H+SM6L2gaSVsq6DUwL+ipxIuCVDIbA8smdXHT X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2026 20:50:56.3123 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a2b806ab-e072-48a6-0edd-08df3f6c5155 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000037B4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8239 In CCA, the ACPI/etc doesn't tell the OS whether the SMMU is a confidential T=1 instance or a normal T=0 one. Instead, it has to be learned by issuing a trusted RSI. Before the kernel can operate the trusted T=1 IOMMU, it also has to validate all the information that it gets from ACPI against the true information that it gets from the RSI call, to ensure the ACPI is correct and prevent substitution attacks. Use RSI_VSMMU_GET_INFO during probe and require the returned register range to match firmware. Then use RSI_ARCH_DEV_ACTIVATE before mapping registers. Currently the driver doesn't support a T=0 SMMU inside a realm. For example it doesn't make the page table allocations into shared memory. If we are in a realm reject any SMMU that is not T=1. Once the SMMU is activated, its DMA will follow the DEV_FLAG_DMA_CC_PRIVATE rules. It must set that flag to ensure its coherent allocations for its own structures are allocated from private memory, not the SWIOTLB shared pool. Also skip Tegra241 CMDQV implementation in the realm world, since realm has the support only for a standard SMMU for now. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 64 ++++++++++++++++++++- 1 file changed, 62 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 6d4520c473086..f3a9436db15e4 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -11,9 +11,11 @@ #include #include +#include #include #include #include +#include #include #include #include @@ -5611,8 +5613,11 @@ static int acpi_smmu_iort_probe_model(struct acpi_iort_node *node, /* * Tegra241 implementation stores its SMMU options and impl_dev * in DSDT. Thus, go through the ACPI tables unconditionally. + * + * Realm doesn't support Tegra CMDQV yet. */ - acpi_smmu_dsdt_probe_tegra241_cmdqv(node, smmu); + if (!is_realm_world()) + acpi_smmu_dsdt_probe_tegra241_cmdqv(node, smmu); break; } @@ -5676,7 +5681,9 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev, smmu->features |= ARM_SMMU_FEAT_COHERENCY; if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) { - tegra_cmdqv_dt_probe(dev->of_node, smmu); + /* Realm doesn't support Tegra CMDQV yet */ + if (!is_realm_world()) + tegra_cmdqv_dt_probe(dev->of_node, smmu); static_branch_enable(&arm_smmu_erratum_repeat_tlbi_cfgi_key); } @@ -5779,6 +5786,53 @@ static struct arm_smmu_device *arm_smmu_impl_probe(struct arm_smmu_device *smmu) return ERR_PTR(ret); } +static void arm_smmu_clear_realm_private(void *dev) +{ + dma_set_cc_private(dev, false); +} + +static int arm_smmu_probe_realm_vsmmu(struct arm_smmu_device *smmu, + const struct resource *res) +{ + struct device *dev = smmu->dev; + unsigned long rsi_ret; + phys_addr_t top; + + /* + * Currently the driver does not support a T=0 SMMU inside a realm. For + * instance it does not make the page table allocations into shared + * memory. If we are in a realm reject any SMMU that is not T=1. + */ + rsi_ret = rsi_vsmmu_get_info(res->start, &top); + if (rsi_ret != RSI_SUCCESS) { + dev_err(dev, "RSI_VSMMU_GET_INFO failed for %pr: %lu\n", res, + rsi_ret); + return -ENODEV; + } + + if (top != res->end + 1) { + dev_err(dev, "VSMMU range %pr ends at %pa\n", res, &top); + return -EINVAL; + } + + rsi_ret = rsi_arch_dev_activate(res->start, RSI_ARCH_DEV_SMMUV3); + if (rsi_ret != RSI_SUCCESS) { + dev_err(dev, "RSI_ARCH_DEV_ACTIVATE failed for %pr: %lu\n", res, + rsi_ret); + return -EIO; + } + + /* + * Once activated, the SMMU DMA follows DEV_FLAG_DMA_CC_PRIVATE so its + * queues and tables are allocated from private memory, not the SWIOTLB + * shared pool. It only translates for a device we've requested the RMM + * to put into T=1. + */ + iommu_device_set_confidential(&smmu->iommu, dev); + + return devm_add_action_or_reset(dev, arm_smmu_clear_realm_private, dev); +} + static int arm_smmu_device_probe(struct platform_device *pdev) { int irq, ret; @@ -5814,6 +5868,12 @@ static int arm_smmu_device_probe(struct platform_device *pdev) } ioaddr = res->start; + if (is_realm_world()) { + ret = arm_smmu_probe_realm_vsmmu(smmu, res); + if (ret) + return ret; + } + /* * Don't map the IMPLEMENTATION DEFINED regions, since they may contain * the PMCG registers which are reserved by the PMU driver. -- 2.43.0