From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6382FC54EBD for ; Fri, 13 Jan 2023 19:28:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229868AbjAMT2Q (ORCPT ); Fri, 13 Jan 2023 14:28:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229806AbjAMT1w (ORCPT ); Fri, 13 Jan 2023 14:27:52 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2959385CA5 for ; Fri, 13 Jan 2023 11:27:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673638071; x=1705174071; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=z3ekLWY5ObJLmIVZrmrckQLOgVzWCWpMqm4KtCSrWtI=; b=AuYw1VS3TEuSWwCJc0nWn4Ch67/gVTLWdLb5z6AmohLmnFn62hh+zXTr lqSPZLexbEcxpoJDwFutGa3b8n8oS+BB1BKte8mw76rX+GrZy3OZqbTiv b/RS3zIEupmwSZNr94ZM5iVpsV76JQpY1T4elaD/MHp6dpbZnR/N+y6Do GTtWI3sCHjcsGJP4YuNgweOQDBLIcu23gfPnsxnaoZEdmAgzOdWqrpP+x 2KBeT+Sdj7CU27XsneSCG9G9CsFHmmHPQInug1mYWVRjR8lN1zY/B3Fhb 77bUG4T4e9vKT4hSqXPy54L4S8lbnuyufzhUMUaZnX/aWDpd7aEEg2Zfx w==; X-IronPort-AV: E=McAfee;i="6500,9779,10589"; a="322777233" X-IronPort-AV: E=Sophos;i="5.97,214,1669104000"; d="scan'208";a="322777233" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jan 2023 11:27:50 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10589"; a="608257464" X-IronPort-AV: E=Sophos;i="5.97,214,1669104000"; d="scan'208";a="608257464" Received: from rerayess-mobl.amr.corp.intel.com (HELO [10.212.13.223]) ([10.212.13.223]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jan 2023 11:27:49 -0800 Message-ID: <68b22ad4-1da0-48e4-a3aa-2b55e5553c01@linux.intel.com> Date: Fri, 13 Jan 2023 11:13:46 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Firefox/102.0 Thunderbird/102.4.2 Subject: Re: [PATCH 03/19] soundwire: amd: register sdw controller dai ops Content-Language: en-US To: "Mukunda,Vijendar" , broonie@kernel.org, vkoul@kernel.org, alsa-devel@alsa-project.org Cc: Basavaraj.Hiregoudar@amd.com, Sunil-kumar.Dommati@amd.com, Mario.Limonciello@amd.com, Mastan.Katragadda@amd.com, arungopal.kondaveeti@amd.com, Bard Liao , Sanyog Kale , open list References: <20230111090222.2016499-1-Vijendar.Mukunda@amd.com> <20230111090222.2016499-4-Vijendar.Mukunda@amd.com> From: Pierre-Louis Bossart In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >>> +static int amd_sdwc_hw_params(struct snd_pcm_substream *substream, >>> + struct snd_pcm_hw_params *params, >>> + struct snd_soc_dai *dai) >>> +{ >>> + struct amd_sdwc_ctrl *ctrl = snd_soc_dai_get_drvdata(dai); >>> + struct sdw_amd_dma_data *dma; >>> + struct sdw_stream_config sconfig; >>> + struct sdw_port_config *pconfig; >>> + int ch, dir; >>> + int ret; >>> + >>> + dma = snd_soc_dai_get_dma_data(dai, substream); >>> + if (!dma) >>> + return -EIO; >>> + >>> + ch = params_channels(params); >>> + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) >>> + dir = SDW_DATA_DIR_RX; >>> + else >>> + dir = SDW_DATA_DIR_TX; >>> + dev_dbg(ctrl->dev, "%s: dir:%d dai->id:0x%x\n", __func__, dir, dai->id); >>> + dma->hw_params = params; >>> + >>> + sconfig.direction = dir; >>> + sconfig.ch_count = ch; >>> + sconfig.frame_rate = params_rate(params); >>> + sconfig.type = dma->stream_type; >>> + >>> + sconfig.bps = snd_pcm_format_width(params_format(params)); >>> + >>> + /* Port configuration */ >>> + pconfig = kzalloc(sizeof(*pconfig), GFP_KERNEL); >>> + if (!pconfig) { >>> + ret = -ENOMEM; >>> + goto error; >>> + } >>> + >>> + pconfig->num = dai->id; >>> + pconfig->ch_mask = (1 << ch) - 1; >>> + ret = sdw_stream_add_master(&ctrl->bus, &sconfig, >>> + pconfig, 1, dma->stream); >>> + if (ret) >>> + dev_err(ctrl->dev, "add master to stream failed:%d\n", ret); >>> + >>> + kfree(pconfig); >>> +error: >>> + return ret; >>> +} >> This looks inspired from intel.c, but you are not programming ANY >> registers here. is this intentional? > We don't have any additional registers to be programmed like intel. ok, this is worthy of a comment. >>> +static const struct snd_soc_dai_ops amd_sdwc_dai_ops = { >>> + .hw_params = amd_sdwc_hw_params, >>> + .hw_free = amd_sdwc_hw_free, >>> + .set_stream = amd_pcm_set_sdw_stream, >> In the first patch there was support for PDM exposed, but here it's PDM >> only? > Didn't get your question. > First patch talks about creating dev nodes for Soundwire managers and > ACP PDM controller based on ACP pin config. Sorry, my comment has a typo. I meant that the first patch exposed PDM support but here you only have PCM?