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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id q12-20020a056512210c00b004b543f38b7csm479198lfr.21.2022.12.02.00.15.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 02 Dec 2022 00:15:27 -0800 (PST) Message-ID: <68bcdf25-e8e3-f817-f213-efb0bce3f43a@linaro.org> Date: Fri, 2 Dec 2022 09:15:25 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [RFT PATCH v2 2/2] arm64: dts: qcom: sdm845: align TLMM pin configuration with DT schema Content-Language: en-US To: Doug Anderson Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Fritz Koenig References: <20221118164201.321147-1-krzysztof.kozlowski@linaro.org> <20221118164201.321147-2-krzysztof.kozlowski@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 02/12/2022 01:50, Doug Anderson wrote: > Hi, > > On Fri, Nov 18, 2022 at 8:42 AM Krzysztof Kozlowski > wrote: >> >> DT schema expects TLMM pin configuration nodes to be named with >> '-state' suffix and their optional children with '-pins' suffix. >> >> Signed-off-by: Krzysztof Kozlowski >> >> --- >> >> Cc: Doug Anderson >> >> Tested on Qualcomm RB3. Please kndly test a bit more on other devices. >> This should not have an functional impact. > > Added Rob Clark and Fritz who are the only people I know that still do > anything with cheza. > > >> - wcd_intr_default: wcd_intr_default { >> + wcd_intr_default: wcd-intr-default-state { >> pins = <54>; > > Not new to your patch, but I'm surprised it truly works to use an > integer for a pin? How does it know that 54 is an integer and not a > string??? Maybe it passes the checks as phandle... Anyway, I'll fix it in separate patch, assuming this is GPIO54. On schematics I see CODEC_INT1_N GPIO_54. > > >> &qup_uart3_default { >> - pinmux { >> - pins = "gpio41", "gpio42", "gpio43", "gpio44"; >> + cts-rts-pins { >> + pins = "gpio41", "gpio42"; >> function = "qup3"; >> }; >> }; > > FWIW, I would have expected that the SoC dtsi file would get a "4-pin" > definition (similar to what you did with qup_uart6_4pin) and then we'd > use that here. Sure. > > >> qup_uart6_4pin: qup-uart6-4pin-state { >> - >> - cts-pins { >> + qup_uart6_4pin_cts: cts-pins { >> pins = "gpio45"; >> function = "qup6"; >> - bias-pull-down; > > After your patch, where is the above bias set for cheza, db845c, > oneplus, shift-axolotl, ...? > > >> }; >> >> - rts-tx-pins { >> + qup_uart6_4pin_rts_tx: rts-tx-pins { >> pins = "gpio46", "gpio47"; >> function = "qup6"; >> - drive-strength = <2>; >> - bias-disable; > > After your patch, where is the above bias / drive-strength set? They don't use 4-pin setup. If they use, I would assume they will override the entries just like sdm850 boards (where I override it to set these). Alternatively I can keep it in DTSI, but it is not really property of the SoC. > > >> }; >> >> - rx-pins { >> + qup_uart6_4pin_rx: rx-pins { >> pins = "gpio48"; >> function = "qup6"; >> - bias-pull-up; > > After your patch, where is the above bias set? Best regards, Krzysztof