From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: mathieu.poirier@linaro.org, acme@kernel.org
Cc: peterz@infradead.org, mingo@redhat.com,
alexander.shishkin@linux.intel.com, jolsa@redhat.com,
namhyung@kernel.org, leo.yan@linaro.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org
Subject: Re: [PATCH v2 01/17] perf tools: Configure contextID tracing in CPU-wide mode
Date: Fri, 7 Jun 2019 10:21:36 +0100 [thread overview]
Message-ID: <68c1c548-33cd-31e8-100d-7ffad008c7b2@arm.com> (raw)
In-Reply-To: <20190524173508.29044-2-mathieu.poirier@linaro.org>
Hi Mathieu,
On 24/05/2019 18:34, Mathieu Poirier wrote:
> When operating in CPU-wide mode being notified of contextID changes is
> required so that the decoding mechanic is aware of the process context
> switch.
>
> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
I am sorry but, I don't remember reviewing this patch in the previous
postings. But here we go.
> ---
> tools/perf/arch/arm/util/cs-etm.c | 126 +++++++++++++++++++++++++-----
> tools/perf/util/cs-etm.h | 12 +++
> 2 files changed, 119 insertions(+), 19 deletions(-)
>
> diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c
> index 911426721170..3912f0bf04ed 100644
> --- a/tools/perf/arch/arm/util/cs-etm.c
> +++ b/tools/perf/arch/arm/util/cs-etm.c
> @@ -35,8 +35,100 @@ struct cs_etm_recording {
> size_t snapshot_size;
> };
>
> static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu);
>
> +static int cs_etm_set_context_id(struct auxtrace_record *itr,
> + struct perf_evsel *evsel, int cpu)
> +{
> + struct cs_etm_recording *ptr;
> + struct perf_pmu *cs_etm_pmu;
> + char path[PATH_MAX];
> + int err = -EINVAL;
> + u32 val;
> +
> + ptr = container_of(itr, struct cs_etm_recording, itr);
> + cs_etm_pmu = ptr->cs_etm_pmu;
> +
> + if (!cs_etm_is_etmv4(itr, cpu))
> + goto out;
> +
> + /* Get a handle on TRCIRD2 */
> + snprintf(path, PATH_MAX, "cpu%d/%s",
> + cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR2]);
> + err = perf_pmu__scan_file(cs_etm_pmu, path, "%x", &val);
> +
> + /* There was a problem reading the file, bailing out */
> + if (err != 1) {
> + pr_err("%s: can't read file %s\n",
> + CORESIGHT_ETM_PMU_NAME, path);
> + goto out;
> + }
> +
> + /*
> + * TRCIDR2.CIDSIZE, bit [9-5], indicates whether contextID tracing
> + * is supported:
> + * 0b00000 Context ID tracing is not supported.
> + * 0b00100 Maximum of 32-bit Context ID size.
> + * All other values are reserved.
> + */
> + val = BMVAL(val, 5, 9);
> + if (!val || val != 0x4) {
> + err = -EINVAL;
> + goto out;
> + }
> +
> + /* All good, let the kernel know */
> + evsel->attr.config |= (1 << ETM_OPT_CTXTID);
> + err = 0;
> +
> +out:
> +
> + return err;
> +}
> +
> +static int cs_etm_set_option(struct auxtrace_record *itr,
> + struct perf_evsel *evsel, u32 option)
> +{
> + int i, err = -EINVAL;
> + struct cpu_map *event_cpus = evsel->evlist->cpus;
> + struct cpu_map *online_cpus = cpu_map__new(NULL);
> +
> + /* Set option of each CPU we have */
> + for (i = 0; i < cpu__max_cpu(); i++) {
> + if (!cpu_map__has(event_cpus, i) ||
> + !cpu_map__has(online_cpus, i))
> + continue;
> +
> + switch (option) {
> + case ETM_OPT_CTXTID:
> + err = cs_etm_set_context_id(itr, evsel, i);
> + if (err)
> + goto out;
> + break;
> + default:
> + goto out;
> + }
> + }
I am not too familiar with the perf tool code. But, isn't there a way
to force the config bit, right from the beginning when the events are
created, when we know that we are doing a CPU wide tracing, along with
the other config bits ?
> + err = 0;
> +out:
> + cpu_map__put(online_cpus);
> + return err;
> +}
> +
> static int cs_etm_parse_snapshot_options(struct auxtrace_record *itr,
> struct record_opts *opts,
> const char *str)
> @@ -105,8 +197,9 @@ static int cs_etm_recording_options(struct auxtrace_record *itr,
> container_of(itr, struct cs_etm_recording, itr);
> struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
> struct perf_evsel *evsel, *cs_etm_evsel = NULL;
> - const struct cpu_map *cpus = evlist->cpus;
> + struct cpu_map *cpus = evlist->cpus;
> bool privileged = (geteuid() == 0 || perf_event_paranoid() < 0);
> + int err = 0;
>
> ptr->evlist = evlist;
> ptr->snapshot_mode = opts->auxtrace_snapshot_mode;
> @@ -241,19 +334,24 @@ static int cs_etm_recording_options(struct auxtrace_record *itr,
>
> /*
> * In the case of per-cpu mmaps, we need the CPU on the
> - * AUX event.
> + * AUX event. We also need the contextID in order to be notified
> + * when a context switch happened.
> */
> - if (!cpu_map__empty(cpus))
> + if (!cpu_map__empty(cpus)) {
> perf_evsel__set_sample_bit(cs_etm_evsel, CPU);
>
> + err = cs_etm_set_option(itr, cs_etm_evsel, ETM_OPT_CTXTID);
> + if (err)
> + goto out;
> + }
> +
> /* Add dummy event to keep tracking */
> if (opts->full_auxtrace) {
> struct perf_evsel *tracking_evsel;
> - int err;
>
> err = parse_events(evlist, "dummy:u", NULL);
> if (err)
> - return err;
> + goto out;
>
> tracking_evsel = perf_evlist__last(evlist);
> perf_evlist__set_tracking_event(evlist, tracking_evsel);
> @@ -266,7 +364,8 @@ static int cs_etm_recording_options(struct auxtrace_record *itr,
> perf_evsel__set_sample_bit(tracking_evsel, TIME);
> }
>
> - return 0;
> +out:
> + return err;
> }
> diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h
> index 0e97c196147a..826c9eedaf5c 100644
> --- a/tools/perf/util/cs-etm.h
> +++ b/tools/perf/util/cs-etm.h
> @@ -103,6 +103,18 @@ struct intlist *traceid_list;
> #define KiB(x) ((x) * 1024)
> #define MiB(x) ((x) * 1024 * 1024)
>
> +/*
> + * Create a contiguous bitmask starting at bit position @l and ending at
> + * position @h. For example
> + * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000.
> + *
> + * Carbon copy of implementation found in $KERNEL/include/linux/bitops.h
> + */
> +#define GENMASK(h, l) \
> + (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
> +
minor nit: Could this be placed in a more generic header file for the other
parts of the perf tool to consume ?
> +#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
> +
Cheers
Suzuki
next prev parent reply other threads:[~2019-06-07 9:21 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-24 17:34 [PATCH v2 00/17] perf tools: Coresight: Add CPU-wide trace support Mathieu Poirier
2019-05-24 17:34 ` [PATCH v2 01/17] perf tools: Configure contextID tracing in CPU-wide mode Mathieu Poirier
2019-06-07 9:21 ` Suzuki K Poulose [this message]
2019-06-07 17:40 ` Mathieu Poirier
2019-06-07 18:20 ` Arnaldo Carvalho de Melo
2019-06-07 19:33 ` Mathieu Poirier
2019-06-17 19:36 ` [tip:perf/core] perf cs-etm: Remove duplicate GENMASK() define, use linux/bits.h instead tip-bot for Arnaldo Carvalho de Melo
2019-06-17 19:20 ` [tip:perf/core] perf cs-etm: Configure contextID tracing in CPU-wide mode tip-bot for Mathieu Poirier
2019-05-24 17:34 ` [PATCH v2 02/17] perf tools: Configure timestsamp generation " Mathieu Poirier
2019-06-07 9:41 ` Suzuki K Poulose
2019-06-07 17:46 ` Mathieu Poirier
2019-06-07 18:34 ` Arnaldo Carvalho de Melo
2019-06-17 19:20 ` [tip:perf/core] perf cs-etm: Configure timestamp " tip-bot for Mathieu Poirier
2019-05-24 17:34 ` [PATCH v2 03/17] perf tools: Configure SWITCH_EVENTS " Mathieu Poirier
2019-06-17 19:21 ` [tip:perf/core] perf cs-etm: " tip-bot for Mathieu Poirier
2019-05-24 17:34 ` [PATCH v2 04/17] perf tools: Add handling of itrace start events Mathieu Poirier
2019-06-17 19:22 ` [tip:perf/core] perf cs-etm: " tip-bot for Mathieu Poirier
2019-05-24 17:34 ` [PATCH v2 05/17] perf tools: Add handling of switch-CPU-wide events Mathieu Poirier
2019-06-17 19:22 ` [tip:perf/core] perf cs-etm: " tip-bot for Mathieu Poirier
2019-05-24 17:34 ` [PATCH v2 06/17] perf tools: Refactor error path in cs_etm_decoder__new() Mathieu Poirier
2019-06-17 19:23 ` [tip:perf/core] perf cs-etm: " tip-bot for Mathieu Poirier
2019-05-24 17:34 ` [PATCH v2 07/17] perf tools: Move packet queue out of decoder structure Mathieu Poirier
2019-06-17 19:24 ` [tip:perf/core] perf cs-etm: " tip-bot for Mathieu Poirier
2019-05-24 17:34 ` [PATCH v2 08/17] perf tools: Fix indentation in function cs_etm__process_decoder_queue() Mathieu Poirier
2019-06-17 19:25 ` [tip:perf/core] perf cs-etm: " tip-bot for Mathieu Poirier
2019-05-24 17:35 ` [PATCH v2 09/17] perf tools: Introduce the concept of trace ID queues Mathieu Poirier
2019-06-17 19:25 ` [tip:perf/core] perf cs-etm: " tip-bot for Mathieu Poirier
2019-05-24 17:35 ` [PATCH v2 10/17] perf tools: Get rid of unused cpu in struct cs_etm_queue Mathieu Poirier
2019-06-17 19:26 ` [tip:perf/core] perf cs-etm: " tip-bot for Mathieu Poirier
2019-05-24 17:35 ` [PATCH v2 11/17] perf tools: Move thread to traceid_queue Mathieu Poirier
2019-06-17 19:27 ` [tip:perf/core] perf cs-etm: " tip-bot for Mathieu Poirier
2019-05-24 17:35 ` [PATCH v2 12/17] perf tools: Move tid/pid " Mathieu Poirier
2019-06-17 19:27 ` [tip:perf/core] perf cs-etm: " tip-bot for Mathieu Poirier
2019-05-24 17:35 ` [PATCH v2 13/17] perf tools: Use traceID aware memory callback API Mathieu Poirier
2019-06-17 19:28 ` [tip:perf/core] perf cs-etm: " tip-bot for Mathieu Poirier
2019-05-24 17:35 ` [PATCH v2 14/17] perf tools: Add support for multiple traceID queues Mathieu Poirier
2019-06-17 19:29 ` [tip:perf/core] perf cs-etm: " tip-bot for Mathieu Poirier
2019-05-24 17:35 ` [PATCH v2 15/17] perf tools: Linking PE contextID with perf thread mechanic Mathieu Poirier
2019-06-17 19:29 ` [tip:perf/core] perf cs-etm: " tip-bot for Mathieu Poirier
2019-05-24 17:35 ` [PATCH v2 16/17] perf tools: Add notion of time to decoding code Mathieu Poirier
2019-06-06 18:50 ` Arnaldo Carvalho de Melo
2019-06-07 14:38 ` Mathieu Poirier
2019-06-17 19:30 ` [tip:perf/core] perf cs-etm: " tip-bot for Mathieu Poirier
2019-05-24 17:35 ` [PATCH v2 17/17] perf tools: Add support for CPU-wide trace scenarios Mathieu Poirier
2019-06-17 19:31 ` [tip:perf/core] perf cs-etm: " tip-bot for Mathieu Poirier
2019-05-31 1:45 ` [PATCH v2 00/17] perf tools: Coresight: Add CPU-wide trace support Leo Yan
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