From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C527311587 for ; Wed, 26 Nov 2025 09:13:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764148414; cv=none; b=uhk1BoZjpOHHP8YI5OhNpM+Imhh1KI1N+HQPrWn+vUMBF0cmGzrzeDca8DHwsNfMl3vlvNNpZ75p5OtMnD5PH0AJZHi/jZDf7QWkeoyUeNZgwuUDEIJpZynGjG8ll5RkKgBOMEdcoBXPLtD3hVDcAwIroOsiDPk6aky2rDRUezQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764148414; c=relaxed/simple; bh=tfIBii/Wk+NhzAbLPhZMs1CNnSy2r2fqC9jyW+2vqqI=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=AEOoKFR9S6BV4d1Sv8G2whlDjcQoU/l0wy25dg6t9k6V9lmlvgSVyQ9uDetG6BvsIjGfAXtNxuQWxIjN/M33+yMmEHXFfw6ACsLXQMJ6O2D2CXfAxu74wpVuowgtKvc1CtZHXi5Mx+vRsLEV5X7KtGzXCbPOQDgUgcMCSrpBx1M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HQNdIfmt; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HQNdIfmt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764148412; x=1795684412; h=from:to:cc:subject:in-reply-to:references:date: message-id:mime-version; bh=tfIBii/Wk+NhzAbLPhZMs1CNnSy2r2fqC9jyW+2vqqI=; b=HQNdIfmtY2o3+Ah944Yvv0Cagzrgx/DSAnSMPgnZaU+07y6KpeKWZM9s 2apXWCCyQFMFzrAle1IrYu8FaXQyptuk/jGDYEleY1CsGCKlUv41LlgF+ kcdjTeTmP5Bwm/zXPz8kenkWpLfa1okT+GtOSU2q/WY5B4a62uu6oLDMN mC9o7IJizN9IXkgmt3LAEmidU8EuR0H4tDtQ0ze2ZJFl87cNt0PNDPJ8Q DiDkBFTKfYZF7ND5VE5eC3/PD/2tSebVdP3RO/cEEP9cgRZghSqNuEE55 pZYDUiSm+AF3ODpyO5VZbzyHTVHUtt5nOjgxGakK08+brB9ws4HiOMMsn A==; X-CSE-ConnectionGUID: MSt8De/JQ5CLWgLTfFerrg== X-CSE-MsgGUID: lxQFBRKZTQylEuLe9ecNgQ== X-IronPort-AV: E=McAfee;i="6800,10657,11624"; a="66064317" X-IronPort-AV: E=Sophos;i="6.20,228,1758610800"; d="scan'208";a="66064317" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Nov 2025 01:13:32 -0800 X-CSE-ConnectionGUID: /ue8e6qfTeO9AlTWpRGkCg== X-CSE-MsgGUID: D1CoxtXXTE+WkinuzrI/hA== X-ExtLoop1: 1 Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.1]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Nov 2025 01:13:26 -0800 From: Jani Nikula To: Yaroslav Bolyukin , Ville =?utf-8?B?U3lyasOkbMOk?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , Christian =?utf-8?Q?K=C3=B6nig?= , Wayne Lin , amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yaroslav Bolyukin Subject: Re: [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension In-Reply-To: <20251126065126.54016-3-iam@lach.pw> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20251126065126.54016-1-iam@lach.pw> <20251126065126.54016-3-iam@lach.pw> Date: Wed, 26 Nov 2025 11:13:23 +0200 Message-ID: <68c55e772424f8e001898cdd1edcf4856820461e@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Wed, 26 Nov 2025, Yaroslav Bolyukin wrote: > Current VESA vendor-specific block parsing expects real block size to be > the same as the defined struct size, use real offsets in conditionals > instead to add struct fields in future commits. > > Signed-off-by: Yaroslav Bolyukin I think this is something we want to backport, since MSO would break with bigger vendor-specific blocks, and that leads to black screens on MSO displays. Cc: stable@vger.kernel.org Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/drm_edid.c | 28 ++++++++++++---------------- > 1 file changed, 12 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > index 64f7a94dd9e4..a52fd6de9327 100644 > --- a/drivers/gpu/drm/drm_edid.c > +++ b/drivers/gpu/drm/drm_edid.c > @@ -6544,7 +6544,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector, > if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) > return; > > - if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { > + if (block->num_bytes < 5) { > drm_dbg_kms(connector->dev, > "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n", > connector->base.id, connector->name); > @@ -6567,24 +6567,20 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector, > break; > } > > - if (!info->mso_stream_count) { > - info->mso_pixel_overlap = 0; > - return; > - } > - > - info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); > - if (info->mso_pixel_overlap > 8) { > + if (info->mso_stream_count) { > + info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); > + if (info->mso_pixel_overlap > 8) { > + drm_dbg_kms(connector->dev, > + "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", > + connector->base.id, connector->name, > + info->mso_pixel_overlap); > + info->mso_pixel_overlap = 8; > + } > drm_dbg_kms(connector->dev, > - "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", > + "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", > connector->base.id, connector->name, > - info->mso_pixel_overlap); > - info->mso_pixel_overlap = 8; > + info->mso_stream_count, info->mso_pixel_overlap); > } > - > - drm_dbg_kms(connector->dev, > - "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", > - connector->base.id, connector->name, > - info->mso_stream_count, info->mso_pixel_overlap); > } > > static void drm_update_vesa_specific_block(struct drm_connector *connector, -- Jani Nikula, Intel