From: Dave Hansen <dave.hansen@intel.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>,
LKML <linux-kernel@vger.kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
Peter Zijlstra <peterz@infradead.org>,
Sohil Mehta <sohil.mehta@intel.com>,
Yuntao Wang <yuntao.wang@linux.dev>,
Zhang Rui <rui.zhang@intel.com>
Subject: Re: x86/apic: Drop useless row from the TSC deadline errata table
Date: Tue, 6 Jan 2026 07:16:40 -0800 [thread overview]
Message-ID: <68eb4ee9-4851-4e87-ae1f-e527597b8c5b@intel.com> (raw)
In-Reply-To: <20250716160824.2167709-1-andrew.cooper3@citrix.com>
On 7/16/25 09:08, Andrew Cooper wrote:
> A microcode revision of 0 is guaranteed to exit
> apic_validate_deadline_timer() early, but a better way is with no
> row at all.
>
> No functional change.
There's one bit of background that is missing which is that the
steppings are unaffected by the erratum. How about this for a changelog?
The later INTEL_SKYLAKE_X steppings (0x5=>0xf, aka. CXL/CPX) are
unaffected by the TSC deadline erratum. There is an entry in the
deadline_match[] table to reflect this. It puts puts a '0' in the table
to represent that all microcode versions >=0 are unaffected by the erratum.
That entry is unnecessary. The best way to indicate that a CPU is
unaffected is to simply omit it from the table.
Remove the stepping >=0x5 entry from the table.
next prev parent reply other threads:[~2026-01-06 15:16 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-16 16:08 x86/apic: Drop useless CXL/CPX " Andrew Cooper
2025-07-17 20:25 ` Sohil Mehta
2025-07-18 10:43 ` Andrew Cooper
2025-07-18 19:25 ` Sohil Mehta
2026-01-06 15:16 ` Dave Hansen [this message]
2026-01-06 18:14 ` [PATCH v2] " Andrew Cooper
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