From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1220E302779 for ; Thu, 19 Feb 2026 21:06:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771535198; cv=none; b=BtxyLoApp/cYAJIe1CCsy2lfweyhWxkT/Ou7nVyKBKvbkKE0KD3PHCtABTI1qxkO3OVL+E+8teIw3+74IC0JE0TZZu7Gad2uzkA4my+Ib2pHYiSGzLp5fVp98rzda/9/DnrWndvk+ZYYON4lBG6U+t2q4nH71NWzoAFV9PUbzec= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771535198; c=relaxed/simple; bh=w3QEOOOED0rszIy3Aj9jX+rNafiDpRJYCSBZ5ofoOGE=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=bBw1rTbKUB7XA82BoNxy02teIjnRR39qeL4rvHpjFDdElX7ITNivHJtVWiBqhdLzKT45Gc7VWCdZOXJF1gwH769PQk/VYzK7AhGYCGTuCsCUO/ku+sJK1LRJFf24xbJEWWVoBFCerFuh6PllpGAbONpYm6O2kqjNE9t2fcqPZ9Y= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=j5MdGRtI; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="j5MdGRtI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1771535197; x=1803071197; h=message-id:subject:from:to:cc:date:in-reply-to: references:content-transfer-encoding:mime-version; bh=w3QEOOOED0rszIy3Aj9jX+rNafiDpRJYCSBZ5ofoOGE=; b=j5MdGRtIMnhsakGHXxvYWxMkGilaOoUjCZ5v38h8MQNplge+s8sF1bv0 KqDGTd2hobUcFKurjcKvBt63RtcZXVhagAUYq9MOHxDXFfnEiYllV1sB8 ao7Y4+dJNzq/QyK5fSAL0CoSylTjzNSx/Gm76pbkpuqmHRa6utm9nd2mR uc0AP6pt7wfRpdKyqtqXkrl/DlyNiaodOD4qyVxI/MHWGuVPFyupWE/jM C0g/3vFpmDT8aLPc2UvEyWuZQruBXTqRGKpaeKMopDhNDxccMPNyoPr3M XRxY9UVmOCSnagCSkX1hXT/l5ve2M9cadA2TGyn78NmuPBdXRNe5ypomV w==; X-CSE-ConnectionGUID: wTtz2VLQRzybrCXtlexR/A== X-CSE-MsgGUID: 2a8OjwMOTkaOYDa7H5Mc1Q== X-IronPort-AV: E=McAfee;i="6800,10657,11706"; a="72695695" X-IronPort-AV: E=Sophos;i="6.21,300,1763452800"; d="scan'208";a="72695695" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2026 13:06:36 -0800 X-CSE-ConnectionGUID: xjtH6YB6SCaKAeJS0j1YHg== X-CSE-MsgGUID: 3ByaCuslTGmXdbm5NIW6hA== X-ExtLoop1: 1 Received: from unknown (HELO [10.241.243.83]) ([10.241.243.83]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2026 13:06:35 -0800 Message-ID: <68ee71c8e36af97f4ba8152ab8707f2d6b6c5c2d.camel@linux.intel.com> Subject: Re: [PATCH v3 15/21] sched/cache: Disable cache aware scheduling for processes with high thread counts From: Tim Chen To: Peter Zijlstra Cc: Ingo Molnar , K Prateek Nayak , "Gautham R . Shenoy" , Vincent Guittot , Chen Yu , Juri Lelli , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Madadi Vineeth Reddy , Hillf Danton , Shrikanth Hegde , Jianyong Wu , Yangyu Chen , Tingyin Duan , Vern Hao , Vern Hao , Len Brown , Aubrey Li , Zhao Liu , Chen Yu , Adam Li , Aaron Lu , Tim Chen , Josh Don , Gavin Guo , Qais Yousef , Libo Chen , linux-kernel@vger.kernel.org Date: Thu, 19 Feb 2026 13:06:35 -0800 In-Reply-To: <20260219165009.GL1395266@noisy.programming.kicks-ass.net> References: <20260219165009.GL1395266@noisy.programming.kicks-ass.net> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.1 (3.58.1-1.fc43) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Thu, 2026-02-19 at 17:50 +0100, Peter Zijlstra wrote: > On Tue, Feb 10, 2026 at 02:18:55PM -0800, Tim Chen wrote: >=20 > > +static bool exceed_llc_nr(struct mm_struct *mm, int cpu) > > +{ > > + int smt_nr =3D 1; > > + > > +#ifdef CONFIG_SCHED_SMT > > + if (sched_smt_active()) > > + smt_nr =3D cpumask_weight(cpu_smt_mask(cpu)); >=20 > cpu_smt_num_threads ? Yes, cpu_smt_num_threads should work. Tim >=20 > > +#endif > > + > > + return !fits_capacity((mm->sc_stat.nr_running_avg * smt_nr), > > + per_cpu(sd_llc_size, cpu)); > > +}