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Fri, 20 Feb 2026 03:02:13 -0600 Received: from [10.24.50.20] (moteen-ubuntu-desk.dhcp.ti.com [10.24.50.20]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 61K90LQ83602457; Fri, 20 Feb 2026 03:00:22 -0600 Message-ID: <696e0132-b54d-45a5-9c88-ba9324f17e26@ti.com> Date: Fri, 20 Feb 2026 14:30:21 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] arm64: dts: ti: k3-am62-lp-sk: Enable internal pulls for MMC0 data pins To: Judith Mendez , Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , , , , Andrew Davis References: <20260212184246.2316659-1-jm@ti.com> <20260212184246.2316659-5-jm@ti.com> Content-Language: en-US From: Moteen Shah In-Reply-To: <20260212184246.2316659-5-jm@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002317:EE_|IA4PR10MB8256:EE_ X-MS-Office365-Filtering-Correlation-Id: a309dd7b-369f-40a5-b981-08de705ebe0d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ywzeJoDbPNJfPj6avs/9/s+bcPJmc9HqPNy8qsxTqAcpCbxwnX/+HrXDbuCDyFcZiokBvDumW9nmNDuDrDvVQ+C7ca7Veg5jIczEgTeuqdWB6x3gGNMTIox7xk5849oUe2xEM1Kh9UpQFKyU+dWo7lqOvrqotfdbH1kK84Qx8TSK3oON9B8x9MS9SLjPun++f+esdsj16CZGMzpt1sTSo/CAAsOTUKhaGKSFTq2R+wqxX5WiTbX+LxW50RZPaDuK2gSiwltCbub+vGpi8SZnVnBmf/jcZuF2h0F7zLaf2lnlQxW9II6eQ9tPCEZbOJV76cX6IsNObkBGqTWran52tQfAkDmFlBOYC09U5QTZB5sTRjLA6mSJFd0kFnRHt4gw6xLHxPFGiBnwP1f2u+F+JiPeMJocYiwQL9MQgetJJsMJjvgCStJh8oYkYIVTeyWp X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Feb 2026 09:02:14.9663 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a309dd7b-369f-40a5-b981-08de705ebe0d X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002317.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA4PR10MB8256 On 13/02/26 00:12, Judith Mendez wrote: > AM62 LP SK board does not have external pullups on MMC0 D1-D7 pins [0], > enable internal pullups considering: > - floating lines violate JDEC spec recommendations > - mismatched pullup resistace between D0 and D1-D7 may cause potential > issues for modes with tighter timing requirements. The different pull-up > values cause different rise/fall times on each data line. > > Fixes: a0b8da04153e ("arm64: dts: ti: k3-am62*: Move eMMC pinmux to top level board file") > [0] https://www.ti.com/lit/zip/SPRR471 > Signed-off-by: Judith Mendez > --- > arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts > index 3e2d8f6695351..8a556fbbe08b7 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts > +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts > @@ -88,13 +88,13 @@ main_mmc0_pins_default: main-mmc0-default-pins { > AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (V3) MMC0_CMD */ > AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (Y1) MMC0_CLK */ > AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (V2) MMC0_DAT0 */ > - AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (V1) MMC0_DAT1 */ > - AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (W2) MMC0_DAT2 */ > - AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (W1) MMC0_DAT3 */ > - AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (Y2) MMC0_DAT4 */ > - AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (W3) MMC0_DAT5 */ > - AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (W4) MMC0_DAT6 */ > - AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (V4) MMC0_DAT7 */ > + AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (V1) MMC0_DAT1 */ > + AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (W2) MMC0_DAT2 */ > + AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (W1) MMC0_DAT3 */ > + AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (Y2) MMC0_DAT4 */ > + AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (W3) MMC0_DAT5 */ > + AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (W4) MMC0_DAT6 */ > + AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (V4) MMC0_DAT7 */ > >; > }; > Same question as of the other patch, won't the mismatch in resistance between D0 and other data lines will cause an issue here. Regards, Moteen