From: Mukesh Ojha <quic_mojha@quicinc.com>
To: Komal Bajaj <quic_kbajaj@quicinc.com>, <agross@kernel.org>,
<andersson@kernel.org>, <konrad.dybcio@linaro.org>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<conor+dt@kernel.org>, <srinivas.kandagatla@linaro.org>
Cc: <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v5 4/6] soc: qcom: Add LLCC support for multi channel DDR
Date: Mon, 24 Jul 2023 18:10:38 +0530 [thread overview]
Message-ID: <6971e2d5-e97d-cb60-473a-e1966e3818cb@quicinc.com> (raw)
In-Reply-To: <20230724084155.8682-5-quic_kbajaj@quicinc.com>
On 7/24/2023 2:11 PM, Komal Bajaj wrote:
> Add LLCC support for multi channel DDR configuration
> based on a feature register.
>
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
> ---
> drivers/soc/qcom/llcc-qcom.c | 26 +++++++++++++++++++++++++-
> 1 file changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 321f8d2079f7..1d2b08dfecea 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -12,6 +12,7 @@
> #include <linux/kernel.h>
> #include <linux/module.h>
> #include <linux/mutex.h>
> +#include <linux/nvmem-consumer.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> #include <linux/regmap.h>
> @@ -997,6 +998,19 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev,
> return ret;
> }
>
> +static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index)
> +{
> + int ret;
> +
> + ret = nvmem_cell_read_u8(&pdev->dev, "multi-chan-ddr", cfg_index);
> + if (ret == -ENOENT || ret == -EOPNOTSUPP) {
> + *cfg_index = 0;
> + return 0;
> + }
> +
> + return ret;
> +}
> +
> static int qcom_llcc_remove(struct platform_device *pdev)
> {
> /* Set the global pointer to a error code to avoid referencing it */
> @@ -1033,6 +1047,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
> const struct qcom_llcc_config *cfg;
> const struct llcc_slice_config *llcc_cfg;
> u32 sz;
> + u8 cfg_index;
> u32 version;
> struct regmap *regmap;
>
> @@ -1050,7 +1065,16 @@ static int qcom_llcc_probe(struct platform_device *pdev)
> }
>
> cfgs = of_device_get_match_data(&pdev->dev);
> - cfg = &cfgs->llcc_config[0];
> + ret = qcom_llcc_get_cfg_index(pdev, &cfg_index);
> + if (ret)
alignment.. ?
-Mukesh
> + goto err;
> +
> + if (cfg_index >= cfgs->num_cfgs) {
> + ret = -EINVAL;
> + goto err;
> + }
> +
> + cfg = &cfgs->llcc_config[cfg_index];
>
> ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
> if (ret)
next prev parent reply other threads:[~2023-07-24 12:40 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-24 8:41 [PATCH v5 0/6] soc: qcom: llcc: Add support for QDU1000/QRU1000 Komal Bajaj
2023-07-24 8:41 ` [PATCH v5 1/6] dt-bindings: cache: qcom,llcc: Add LLCC compatible " Komal Bajaj
2023-07-24 9:51 ` Krzysztof Kozlowski
2023-07-24 8:41 ` [PATCH v5 2/6] soc: qcom: llcc: Refactor llcc driver to support multiple configuration Komal Bajaj
2023-07-24 12:28 ` Mukesh Ojha
2023-07-24 13:26 ` Krzysztof Kozlowski
2023-07-24 16:14 ` Mukesh Ojha
2023-07-24 16:11 ` Mukesh Ojha
2023-08-02 8:53 ` Komal Bajaj
2023-07-24 8:41 ` [PATCH v5 3/6] nvmem: core: Add stub for nvmem_cell_read_u8 Komal Bajaj
2023-07-24 12:36 ` Mukesh Ojha
2023-08-02 8:53 ` Komal Bajaj
2023-07-24 8:41 ` [PATCH v5 4/6] soc: qcom: Add LLCC support for multi channel DDR Komal Bajaj
2023-07-24 12:40 ` Mukesh Ojha [this message]
2023-08-02 8:54 ` Komal Bajaj
2023-07-24 8:41 ` [PATCH v5 5/6] soc: qcom: llcc: Updating the macro name Komal Bajaj
2023-07-24 12:41 ` Mukesh Ojha
2023-07-24 12:48 ` Konrad Dybcio
2023-08-02 8:55 ` Komal Bajaj
2023-07-24 8:41 ` [PATCH v5 6/6] soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support Komal Bajaj
2023-07-24 12:45 ` Mukesh Ojha
2023-07-24 12:55 ` Konrad Dybcio
2023-08-02 9:00 ` Komal Bajaj
2023-08-02 8:57 ` Komal Bajaj
2023-07-24 12:54 ` Konrad Dybcio
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