From: "Nícolas F. R. A. Prado" <nfraprado@collabora.com>
To: "CK Hu (胡俊光)" <ck.hu@mediatek.com>,
"tzimmermann@suse.de" <tzimmermann@suse.de>,
"chunkuang.hu@kernel.org" <chunkuang.hu@kernel.org>,
"simona@ffwll.ch" <simona@ffwll.ch>,
"AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
"airlied@gmail.com" <airlied@gmail.com>,
"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
"maarten.lankhorst@linux.intel.com"
<maarten.lankhorst@linux.intel.com>,
"mripard@kernel.org" <mripard@kernel.org>,
"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>
Cc: "dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
Daniel Stone <daniels@collabora.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Ariel D'Alessandro <ariel.dalessandro@collabora.com>,
"kernel@collabora.com" <kernel@collabora.com>
Subject: Re: [PATCH 10/11] drm/mediatek: ovl: Enable support for R2R Color Space Conversion
Date: Wed, 18 Mar 2026 09:18:28 -0400 [thread overview]
Message-ID: <698d1d3f41d7931e6447545394757f71b9ebc597.camel@collabora.com> (raw)
In-Reply-To: <2ce1ed408fd87366d3abc1e79bc3d1dc055af91b.camel@mediatek.com>
On Tue, 2026-03-03 at 07:16 +0000, CK Hu (胡俊光) wrote:
> On Tue, 2025-12-23 at 16:44 -0300, Nícolas F. R. A. Prado wrote:
> > External email : Please do not click links or open attachments
> > until you have verified the sender or the content.
> >
> >
> > The OVL hardware allows applying a 3x3 matrix transformation for
> > each
> > layer through the 'RGB to RGB Color Space Conversion' (R2R CSC)
> > setting.
> > Implement support for it and expose it as a colorop through the DRM
> > plane color pipeline uAPI.
> >
> > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 55
> > ++++++++++++++++++++++++++++++++-
> > 1 file changed, 54 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > index a70092c792a9..c8a2b1b13035 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > @@ -4,6 +4,7 @@
> > */
> >
> > #include <drm/drm_blend.h>
> > +#include <drm/drm_color_mgmt.h>
> > #include <drm/drm_colorop.h>
> > #include <drm/drm_fourcc.h>
> > #include <drm/drm_framebuffer.h>
> > @@ -52,6 +53,7 @@
> > #define OVL_CON_CLRFMT_10_BIT (1)
> > #define DISP_REG_OVL_WCG_CFG1 0x2d8
> > #define IGAMMA_EN(layer) BIT(0 + 4 *
> > (layer))
> > +#define CSC_EN(layer) BIT(1 + 4 *
> > (layer))
> > #define GAMMA_EN(layer)
> > BIT(2 + 4 * (layer))
> > #define DISP_REG_OVL_WCG_CFG2 0x2dc
> > #define IGAMMA_MASK(layer)
> > GENMASK((layer) * 4 + 1, (layer) * 4)
> > @@ -62,6 +64,7 @@
> > #define GAMMA_BT709 1
> > #define GAMMA_BT2020 2
> > #define GAMMA_HLG 3
> > +#define DISP_REG_OVL_R2R_PARA(layer) (0x500 + (layer) *
> > 0x40)
> > #define DISP_REG_OVL_ADDR_MT8173 0x0f40
> > #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr
> > + 0x20 * (n))
> > #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr
> > + 0x20 * (n) + 0x04)
> > @@ -579,11 +582,44 @@ static void mtk_ovl_apply_igamma(struct
> > mtk_disp_ovl *ovl, unsigned int idx,
> > IGAMMA_EN(idx));
> > }
> >
> > +static void mtk_ovl_write_r2r_para(struct mtk_disp_ovl *ovl,
> > unsigned int idx,
> > + struct drm_color_ctm *ctm,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + unsigned int i;
> > + u64 val;
> > +
> > + for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) {
> > + val = drm_color_ctm_s31_32_to_qm_n(ctm->matrix[i],
> > 5, 18);
> > + mtk_ddp_write(cmdq_pkt, val, &ovl->cmdq_reg, ovl-
> > >regs,
> > + DISP_REG_OVL_R2R_PARA(idx) + i * 4);
> > + }
> > +}
> > +
> > +static void mtk_ovl_apply_r2r_csc(struct mtk_disp_ovl *ovl,
> > unsigned int idx,
> > + struct drm_colorop *colorop,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct drm_color_ctm *ctm;
> > +
> > + if (colorop->state->data && colorop->state->data->data) {
> > + ctm = (struct drm_color_ctm *)colorop->state->data-
> > >data;
> > + mtk_ovl_write_r2r_para(ovl, idx, ctm, cmdq_pkt);
> > + }
> > +
>
> If bypass imply colorop->state->data->data is NULL, nothing need to
> change.
> If bypass does not imply colorop->state->data->data is NULL, I would
> like to disable CSC first then clear r2r parameter.
bypass does not imply NULL data. But even when setting the CSC block to
be bypassed, we don't want to clear its parameters, we want to set the
parameters passed by userspace in this atomic commit, if any, and if
not we want to keep the current parameters, in case they have been set
in a previous atomic commit, so that a future commit setting bypass=0
will have the parameters previously set, without having to pass them
again.
Thanks,
Nícolas
next prev parent reply other threads:[~2026-03-18 13:19 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-23 19:44 [PATCH 00/11] Plane Color Pipeline support for MediaTek Nícolas F. R. A. Prado
2025-12-23 19:44 ` [PATCH 01/11] drm/mediatek: Introduce DDP plane_colorops_init() hook Nícolas F. R. A. Prado
2026-02-06 10:07 ` AngeloGioacchino Del Regno
2026-02-06 14:13 ` Nícolas F. R. A. Prado
2025-12-23 19:44 ` [PATCH 02/11] drm/mediatek: Initialize colorops when creating plane Nícolas F. R. A. Prado
2026-02-06 10:07 ` AngeloGioacchino Del Regno
2025-12-23 19:44 ` [PATCH 03/11] drm/mediatek: ovl: Add supports_plane_colorops flag Nícolas F. R. A. Prado
2025-12-24 2:17 ` Macpaul Lin (林智斌)
2026-02-06 10:07 ` AngeloGioacchino Del Regno
2026-02-06 14:10 ` Nícolas F. R. A. Prado
2025-12-23 19:44 ` [PATCH 04/11] drm/mediatek: ovl: Enable per-plane color operations on MT8195 Nícolas F. R. A. Prado
2025-12-24 2:19 ` Macpaul Lin (林智斌)
2026-02-06 10:07 ` AngeloGioacchino Del Regno
2026-02-06 14:11 ` Nícolas F. R. A. Prado
2025-12-23 19:44 ` [PATCH 05/11] drm/mediatek: ovl: Implement support for Inverse Gamma Nícolas F. R. A. Prado
2026-02-25 8:54 ` CK Hu (胡俊光)
2026-02-25 9:40 ` CK Hu (胡俊光)
2025-12-23 19:44 ` [PATCH 06/11] drm/mediatek: Add plane_colorops_init() DDP hook for OVL Nícolas F. R. A. Prado
2025-12-24 2:20 ` Macpaul Lin (林智斌)
2026-02-25 8:58 ` CK Hu (胡俊光)
2025-12-23 19:44 ` [PATCH 07/11] drm/colorop: Introduce HLG EOTF Nícolas F. R. A. Prado
2025-12-24 2:21 ` Macpaul Lin (林智斌)
2026-02-06 8:51 ` Pekka Paalanen
2026-02-06 14:02 ` Nícolas F. R. A. Prado
2025-12-23 19:44 ` [PATCH 08/11] drm/mediatek: ovl: Implement support for Gamma Nícolas F. R. A. Prado
2026-03-03 6:53 ` CK Hu (胡俊光)
2026-03-18 13:04 ` Nícolas F. R. A. Prado
2025-12-23 19:44 ` [PATCH 09/11] drm/colorop: Introduce 3x3 Matrix Nícolas F. R. A. Prado
2026-02-06 9:27 ` Pekka Paalanen
2026-02-06 14:05 ` Nícolas F. R. A. Prado
2025-12-23 19:44 ` [PATCH 10/11] drm/mediatek: ovl: Enable support for R2R Color Space Conversion Nícolas F. R. A. Prado
2026-03-03 7:16 ` CK Hu (胡俊光)
2026-03-18 13:18 ` Nícolas F. R. A. Prado [this message]
2025-12-23 19:44 ` [PATCH 11/11] drm/mediatek: Check 3x3 Matrix colorop has DATA set Nícolas F. R. A. Prado
2026-03-03 7:21 ` CK Hu (胡俊光)
2025-12-29 18:53 ` [PATCH 00/11] Plane Color Pipeline support for MediaTek Shengyu Qu
2026-01-01 12:37 ` Shengyu Qu
2026-01-02 18:40 ` Harry Wentland
2026-02-06 9:09 ` Pekka Paalanen
2026-02-06 13:28 ` Nícolas F. R. A. Prado
2026-02-26 6:24 ` CK Hu (胡俊光)
2026-02-26 10:26 ` AngeloGioacchino Del Regno
2026-02-26 10:51 ` AngeloGioacchino Del Regno
2026-03-18 12:43 ` Nícolas F. R. A. Prado
2026-01-07 20:01 ` Xaver Hugl
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