From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39C2326B08F for ; Sun, 2 Aug 2026 16:17:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785687454; cv=none; b=Gu1PvhHfBLHM91lrlRZ2puhzNze9OpPcabj7vkPZmjQZD4o+ebnNMQjQfLSLXRYne/MXIxPSLVbjghN++ufOhNbwG73purVVSau82VWo0lyJEZduHuoqRwHVXTxxX/QA43KViRsyfnXJWWF1KObFk4f2K4wQj6u7hhW73znm7NM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785687454; c=relaxed/simple; bh=rn6bXyktBI4cwsuN+/U6V6RZ/37UVI7YWJu7lOLslEU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rnCc3Im285zIYE0+MNWwHdCRSVqWu/FweT3H1IvDtB+wjC+alNqSL/5SNsYxM6d0N1PkK2xCZZuWweCSvl6DUNSkTd5CVDLmNB8HA095dwy3emcGSivdQhlpbi7bN+mTx+b5KoZZoJ4uhmWMTCOkb5+uTEsQ1niIRtfiyuy5gp8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Np6ATrWx; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Np6ATrWx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785687453; x=1817223453; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rn6bXyktBI4cwsuN+/U6V6RZ/37UVI7YWJu7lOLslEU=; b=Np6ATrWxKIAo+qJfj5KM90KvlTuzFEl+yintYpKe00/aC47c5aYQ9QcD 5Mt6cgw0opuJMat9PX16vvNWnugc9c6yXxAQnaQ/t8aQF1By/NP23cBIn /bdSYhmiRBU6Plh2tEdxKZMIcB7pSQf14d1fu8QHHb/EF6K3X8fM3hr3J xhywBNyWjZZtTNrbXW3vqWoMa9XA7pZNyjzSy6j7x1gnMIwhdffP1XWsw /laHYg0AU3x4EnXygNP5k6TsrxghZxOnsM4qDwvTLrENiE4io63Un1Jhv Pp/r9QgTqr4XCL/iYL5f3Hh6fwo88BKB+itnkbAl3OLwV+Frd7qc+SmTe g==; X-CSE-ConnectionGUID: AXJf8FP9S6WdvDM3UFPrjg== X-CSE-MsgGUID: 0bY0Ox9WSJGUOWJEkow2nA== X-IronPort-AV: E=McAfee;i="6800,10657,11863"; a="86276313" X-IronPort-AV: E=Sophos;i="6.25,200,1779174000"; d="scan'208";a="86276313" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Aug 2026 09:17:32 -0700 X-CSE-ConnectionGUID: 3rrzWflVS/GXp3QR4wUshg== X-CSE-MsgGUID: RwVJXJOjSBebtX6BFCss+g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,200,1779174000"; d="scan'208";a="285634197" Received: from chenyu-dev.sh.intel.com ([10.239.62.107]) by fmviesa001.fm.intel.com with ESMTP; 02 Aug 2026 09:17:30 -0700 From: Chen Yu To: Reinette Chatre , Tony Luck Cc: Ben Horgan , "James Morse" , Dave Martin , Babu Moger , Fenghua Yu , Borislav Petkov , Thomas Gleixner , "Dave Hansen" , Peter Newman , chen.yu@linux.dev, x86@kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 26/31] x86/resctrl: Allow control writes from any CPU for MMIO controllers Date: Mon, 3 Aug 2026 00:07:48 +0800 Message-Id: <698e1e2d342df6e726cd5b5952923cecbd94c805.1785680802.git.yu.c.chen@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Programming a control that lives in domain-local MSR space must run on a CPU that belongs to the target domain, so resctrl_arch_update_domains() issues the hw_update() via an IPI. MMIO based controls (e.g. the ERDT MARC registers) have no such affinity requirement and can be programmed from the current CPU, making the IPI pure overhead. Introduce RESCTRL_CTRL_FLAG_ANY_CPU to describe a control whose hardware can be programmed from any CPU, mirroring the mon_evt::any_cpu flag used on the monitoring read path. Set it on the MARC controllers at creation time. Signed-off-by: Chen Yu --- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 11 ++++++++++- arch/x86/kernel/cpu/resctrl/erdt.c | 2 ++ include/linux/resctrl.h | 1 + 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c index 1dd59d36e86c..7bacb8bf2e27 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -19,6 +19,15 @@ #include "internal.h" +static void ctrl_hw_update(struct resctrl_ctrl *ctrl, struct rdt_ctrl_domain *d, + struct hw_param *m) +{ + if (ctrl->flags & RESCTRL_CTRL_FLAG_ANY_CPU) + rdt_ctrl_update(m); + else + smp_call_function_any(&d->hdr.cpu_mask, rdt_ctrl_update, m, 1); +} + int resctrl_arch_update_one(struct rdt_resource *r, struct resctrl_ctrl *ctrl, struct rdt_ctrl_domain *d, u32 closid, enum resctrl_conf_type t, u32 cfg_val) @@ -81,7 +90,7 @@ static void _resctrl_arch_update_domains(struct rdt_resource *r, } } if (hw_param.res) - smp_call_function_any(&d->hdr.cpu_mask, rdt_ctrl_update, &hw_param, 1); + ctrl_hw_update(ctrl, d, &hw_param); } } diff --git a/arch/x86/kernel/cpu/resctrl/erdt.c b/arch/x86/kernel/cpu/resctrl/erdt.c index c25aff805b12..8f087defffac 100644 --- a/arch/x86/kernel/cpu/resctrl/erdt.c +++ b/arch/x86/kernel/cpu/resctrl/erdt.c @@ -369,6 +369,8 @@ __init bool erdt_get_mem_config(struct rdt_resource *r) hw_ctrl->r_ctrl.scalar.unit = RESCTRL_CTRL_UNIT_ALL; hw_ctrl->hw_update = marc_hw_update; + /* MARC controls live in MMIO, program from any CPU. */ + hw_ctrl->r_ctrl.flags |= RESCTRL_CTRL_FLAG_ANY_CPU; list_add_tail(&hw_ctrl->r_ctrl.entry, &r->controls); } } diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 3969db01f4cc..8260b09aa323 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -386,6 +386,7 @@ resctrl_ctrl_name_region(unsigned int region, unsigned int type) /* Flags for rdt_resource::flags and resctrl_ctrl::flags */ #define RESCTRL_CTRL_FLAG_LINEAR BIT(0) #define RESCTRL_CTRL_FLAG_SPARSE_BITMASKS BIT(1) +#define RESCTRL_CTRL_FLAG_ANY_CPU BIT(2) /** * struct resctrl_ctrl - A resource control -- 2.43.0