From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755270AbeARQh5 (ORCPT ); Thu, 18 Jan 2018 11:37:57 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:65428 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754754AbeARQhz (ORCPT ); Thu, 18 Jan 2018 11:37:55 -0500 From: Philippe CORNU To: Gabriel FERNANDEZ , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre TORGUE , Michael Turquette , Stephen Boyd , Nicolas Pitre , "daniel.thompson@linaro.org" CC: "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , "gabriel.fernandez.st@gmail.com" Subject: Re: [PATCH 2/2] clk: stm32: Add DSI clock for STM32F469 Board Thread-Topic: [PATCH 2/2] clk: stm32: Add DSI clock for STM32F469 Board Thread-Index: AQHTkGuZAbqSRrxtIEejE32pmXpm5KN5w6YA Date: Thu, 18 Jan 2018 16:37:28 +0000 Message-ID: <69b40967-b334-5e94-0d57-e23944c30b17@st.com> References: <1516286980-8603-1-git-send-email-gabriel.fernandez@st.com> <1516286980-8603-3-git-send-email-gabriel.fernandez@st.com> In-Reply-To: <1516286980-8603-3-git-send-email-gabriel.fernandez@st.com> Accept-Language: fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.45] Content-Type: text/plain; charset="utf-8" Content-ID: <28954DDC045C164C861CBDD84B76AB5A@st.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-01-18_08:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id w0IGcERf019881 Hi Gabriel, Tested successfully on f469 disco board. Tested-by: Philippe Cornu Many thanks, Philippe :-) On 01/18/2018 03:49 PM, gabriel.fernandez@st.com wrote: > From: Gabriel Fernandez > > This patch adds DSI clock for STM32F469 board > > Signed-off-by: Gabriel Fernandez > --- > drivers/clk/clk-stm32f4.c | 11 ++++++++++- > include/dt-bindings/clock/stm32fx-clock.h | 3 ++- > 2 files changed, 12 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c > index da44f8d..3c28798 100644 > --- a/drivers/clk/clk-stm32f4.c > +++ b/drivers/clk/clk-stm32f4.c > @@ -521,7 +521,7 @@ struct stm32f4_pll_data { > }; > > static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = { > - { PLL, 50, { "pll", "pll-q", NULL } }, > + { PLL, 50, { "pll", "pll-q", "pll-r" } }, > { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } }, > { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } }, > }; > @@ -1047,6 +1047,8 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name, > "no-clock", "lse", "lsi", "hse-rtc" > }; > > +static const char *dsi_parent[2] = { NULL, "pll-r" }; > + > static const char *lcd_parent[1] = { "pllsai-r-div" }; > > static const char *i2s_parents[2] = { "plli2s-r", NULL }; > @@ -1156,6 +1158,12 @@ struct stm32f4_clk_data { > NO_GATE, 0, > 0 > }, > + { > + CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent), > + STM32F4_RCC_DCKCFGR, 29, 1, > + STM32F4_RCC_APB2ENR, 27, > + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT > + }, > }; > > static const struct stm32_aux_clk stm32f746_aux_clk[] = { > @@ -1450,6 +1458,7 @@ static void __init stm32f4_rcc_init(struct device_node *np) > stm32f4_gate_map = data->gates_map; > > hse_clk = of_clk_get_parent_name(np, 0); > + dsi_parent[0] = hse_clk; > > i2s_in_clk = of_clk_get_parent_name(np, 1); > > diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h > index 4d523b0..58d8b51 100644 > --- a/include/dt-bindings/clock/stm32fx-clock.h > +++ b/include/dt-bindings/clock/stm32fx-clock.h > @@ -35,8 +35,9 @@ > #define CLK_SAIQ_PDIV 13 > #define CLK_HSI 14 > #define CLK_SYSCLK 15 > +#define CLK_F469_DSI 16 > > -#define END_PRIMARY_CLK 16 > +#define END_PRIMARY_CLK 17 > > #define CLK_HDMI_CEC 16 > #define CLK_SPDIF 17 >