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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-40fb985e080sm2143861f8f.24.2025.09.25.02.02.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Sep 2025 02:02:17 -0700 (PDT) Message-ID: <69e8c15d-108e-4832-849e-a23c7ddfe625@linaro.org> Date: Thu, 25 Sep 2025 10:02:15 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/9] dt-bindings: clock: qcom: Add Kaanapali video clock controller To: Jingyi Wang , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Vladimir Zapolskiy , Jagadeesh Kona , Dmitry Baryshkov , Maxime Coquelin , Alexandre Torgue , Taniya Das , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com References: <20250924-knp-mmclk-v1-0-d7ea96b4784a@oss.qualcomm.com> <20250924-knp-mmclk-v1-4-d7ea96b4784a@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: <20250924-knp-mmclk-v1-4-d7ea96b4784a@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 25/09/2025 00:56, Jingyi Wang wrote: > From: Taniya Das > > Add device tree bindings for the video clock controller on Qualcomm > Kaanapali SoC. > > Signed-off-by: Taniya Das > Signed-off-by: Jingyi Wang > --- > .../bindings/clock/qcom,sm8450-videocc.yaml | 3 ++ > include/dt-bindings/clock/qcom,kaanapali-videocc.h | 58 ++++++++++++++++++++++ > 2 files changed, 61 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > index b31bd8335529..e6beebd6a36e 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > @@ -15,6 +15,7 @@ description: | > domains on SM8450. > > See also: > + include/dt-bindings/clock/qcom,kaanapali-videocc.h > include/dt-bindings/clock/qcom,sm8450-videocc.h > include/dt-bindings/clock/qcom,sm8650-videocc.h > include/dt-bindings/clock/qcom,sm8750-videocc.h > @@ -22,6 +23,7 @@ description: | > properties: > compatible: > enum: > + - qcom,kaanapali-videocc > - qcom,sm8450-videocc > - qcom,sm8475-videocc > - qcom,sm8550-videocc > @@ -61,6 +63,7 @@ allOf: > compatible: > contains: > enum: > + - qcom,kaanapali-videocc > - qcom,sm8450-videocc > - qcom,sm8550-videocc > - qcom,sm8750-videocc > diff --git a/include/dt-bindings/clock/qcom,kaanapali-videocc.h b/include/dt-bindings/clock/qcom,kaanapali-videocc.h > new file mode 100644 > index 000000000000..cc0d41b895c9 > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,kaanapali-videocc.h > @@ -0,0 +1,58 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_KAANAPALI_H > +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_KAANAPALI_H > + > +/* VIDEO_CC clocks */ > +#define VIDEO_CC_AHB_CLK 0 > +#define VIDEO_CC_AHB_CLK_SRC 1 > +#define VIDEO_CC_MVS0_CLK 2 > +#define VIDEO_CC_MVS0_CLK_SRC 3 > +#define VIDEO_CC_MVS0_FREERUN_CLK 4 > +#define VIDEO_CC_MVS0_SHIFT_CLK 5 > +#define VIDEO_CC_MVS0_VPP0_CLK 6 > +#define VIDEO_CC_MVS0_VPP0_FREERUN_CLK 7 > +#define VIDEO_CC_MVS0_VPP1_CLK 8 > +#define VIDEO_CC_MVS0_VPP1_FREERUN_CLK 9 > +#define VIDEO_CC_MVS0A_CLK 10 > +#define VIDEO_CC_MVS0A_CLK_SRC 11 > +#define VIDEO_CC_MVS0A_FREERUN_CLK 12 > +#define VIDEO_CC_MVS0B_CLK 13 > +#define VIDEO_CC_MVS0B_CLK_SRC 14 > +#define VIDEO_CC_MVS0B_FREERUN_CLK 15 > +#define VIDEO_CC_MVS0C_CLK 16 > +#define VIDEO_CC_MVS0C_CLK_SRC 17 > +#define VIDEO_CC_MVS0C_FREERUN_CLK 18 > +#define VIDEO_CC_MVS0C_SHIFT_CLK 19 > +#define VIDEO_CC_PLL0 20 > +#define VIDEO_CC_PLL1 21 > +#define VIDEO_CC_PLL2 22 > +#define VIDEO_CC_PLL3 23 > +#define VIDEO_CC_SLEEP_CLK 24 > +#define VIDEO_CC_TS_XO_CLK 25 > +#define VIDEO_CC_XO_CLK 26 > +#define VIDEO_CC_XO_CLK_SRC 27 > + > +/* VIDEO_CC power domains */ > +#define VIDEO_CC_MVS0A_GDSC 0 > +#define VIDEO_CC_MVS0_GDSC 1 > +#define VIDEO_CC_MVS0_VPP1_GDSC 2 > +#define VIDEO_CC_MVS0_VPP0_GDSC 3 > +#define VIDEO_CC_MVS0C_GDSC 4 > + > +/* VIDEO_CC resets */ > +#define VIDEO_CC_INTERFACE_BCR 0 > +#define VIDEO_CC_MVS0_BCR 1 > +#define VIDEO_CC_MVS0_VPP0_BCR 2 > +#define VIDEO_CC_MVS0_VPP1_BCR 3 > +#define VIDEO_CC_MVS0A_BCR 4 > +#define VIDEO_CC_MVS0C_CLK_ARES 5 > +#define VIDEO_CC_MVS0C_BCR 6 > +#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 7 > +#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 8 > +#define VIDEO_CC_XO_CLK_ARES 9 > + > +#endif > Reviewed-by: Bryan O'Donoghue