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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b412dec1sm758405a12.30.2025.12.04.01.34.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Dec 2025 01:35:01 -0800 (PST) Message-ID: <69f7f357-d328-4559-be8a-81a9df790f0a@oss.qualcomm.com> Date: Thu, 4 Dec 2025 10:34:58 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 08/11] clk: qcom: dispcc: Add support for display clock controller Kaanapali To: Taniya Das , Dmitry Baryshkov Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Maxime Coquelin , Alexandre Torgue , Vladimir Zapolskiy , Konrad Dybcio , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org References: <20251125-kaanapali-mmcc-v2-v2-0-fb44e78f300b@oss.qualcomm.com> <20251125-kaanapali-mmcc-v2-v2-8-fb44e78f300b@oss.qualcomm.com> <8d0ec7fc-6eb0-4b71-8e0f-3deaf1f489d6@oss.qualcomm.com> <75e53a37-0fd2-41d6-92bc-fb4ad5856829@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <75e53a37-0fd2-41d6-92bc-fb4ad5856829@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: oYgjQXDI6WScWbuaqBsZ6d3EZFasDP_V X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA0MDA3NyBTYWx0ZWRfX/YWyOtJQmpKp 9taaMACmpu6s47oyXZxkY/4ZiksB8VAGd6SZFXtA/qE/Sdh/BOdWrLlXvIUxIuUKMPbaCoxEUsk IWVh6khR0bk5mEBZr47/TNWFJjDPVmBaGn98GbmXvRGNZJvZCUiHApXnVMTHoVTK/GoZry1nNXF 3LI1ua7Bf4IzBhcb73ciPhLZ3YNogDpXSM8aGgjIFruLdsfOw8B1PZRbEQAStqVjsttJTL8mvsZ tDLmsVGtlJkriazPgEmYZhnvXJ+oMv63BSdXfpluijVVc/uuiwoTOCnjKpraystj1Vf4Z6p/M+A dlybv1VosdK3fq+XVwBA9XlPOhObc94PDMxHy1Ucm4bPeTpIe1ncBAlezY0gSqrFBrIcu0ZNZXL 19+s0/mqP9Rf/UOu2qRtUXd6r6O/SA== X-Proofpoint-GUID: oYgjQXDI6WScWbuaqBsZ6d3EZFasDP_V X-Authority-Analysis: v=2.4 cv=V5lwEOni c=1 sm=1 tr=0 ts=693155c7 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=gmcpGffKwdJZmXMFCqgA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-04_02,2025-12-03_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 priorityscore=1501 adultscore=0 malwarescore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512040077 On 12/4/25 8:14 AM, Taniya Das wrote: > > > On 12/1/2025 6:50 PM, Konrad Dybcio wrote: >> On 11/26/25 1:09 AM, Dmitry Baryshkov wrote: >>> On Tue, Nov 25, 2025 at 11:15:17PM +0530, Taniya Das wrote: >>>> Support the clock controller driver for Kaanapali to enable display SW to >>>> be able to control the clocks. >>>> >>>> Signed-off-by: Taniya Das >>>> --- >> >> [...] >> >>>> +/* 257.142858 MHz Configuration */ >>> >>> This is a bit strange frequency for the boot config. > > The lowest PLL configuration is used as boot config based on the > MDP_CLK_SRC clock requirement. The PLLs on Kaanapali can support these > lower frequencies as well. > > >> The frequency map lists this odd cookie as the lowest predefined config, >> perhaps it was pulled from there. >> > > Correct Konrad. > >> More interestingly, the only consumer of this PLL (MDP_CLK_SRC) makes no >> effort to use the m/n/d registers, instead relying on the PLL to re-clock >> for its ratesetting with a fixed divider of 3 (and div1 @ XO rate). >> > > The m/n is not preferred in the cases where the PLL needs to slew to > derive a new VCO frequency. That is the reason to keep the divider > constant as much as possible to derive a particular frequency. OK this is roughly what I expected, thanks for the explanation. > >> 257.142858 * 3 = 771.428574 over-drives MDP_CLK_SRC, FWIW. >> > > The lowest frequency requirement is 85.7MHz and the frequency is derived > using > 257.142858 (PLL VCO) / 3 (RCG Div) = 85.714286 MHz > > there is no over-drive at RCG of MDP. Sorry, you're obviously right, I don't know how I got it backwards.. >> Taniya, we've seen something like this in camera too. Is there a reason >> the frequency is being set this way? >> > > We start with the lowest frequency to configure the PLL and frequency > requirements are decided based on usecases. I meant the rate-change-through-PLL-reclocking, but you've answered that above Konrad